Tegra124/Jetson-tk1 Hardware Interrupt Handling/Architecture Question

The reason I’m interested in this is because there seems to be a flaw in network bridge code which I can’t debug without a working JTAG debugger configuration…and this may be related to the bug.

In the past I’ve worked with Intel CPU motherboards which would handle hardware interrupts only on the first CPU; to this end, an IO-APIC was added to those motherboards which enabled all CPUs to handle hardware IRQs (but the kernel has to use the IO-APIC).

In /proc/interrupts, I see only CPU0 handling interrupts. Can someone tell me if this is a kernel limitation, or if this is instead a hardware limitation (e.g., similar to needing an IO-APIC for other CPUs to handle hardware IRQs)? Is the first CPU core the only core which can handle hardware IRQs? Is there a way to enable all CPU cores to handle hardware IRQs?

Currently the issue I’m working on is a system freeze from network bridge code which completely breaks even sysrq response. The serial console has indicated even the eMMC has stopped responding during this time, and I am thinking of hardware interrupt starvation. If multiple cores could handle hardware interrupts the system might remain responsive during the failure.

Bump