the v4l2 cmd and gst-launch-1.0 can’t work
the dmesg log is the same as before, but the tracing log is different, only print the “rtos_queue_send_from_isr_failed” log
hello chengejun1984,
I’m also wondering what’s the capture result via Argus;
while configure DT as 2560x800, did you see any difference (especially top and bottom of the image) with/without vblank=110?
thanks
hello jerry
I can’t see any different between with/without vblank in the image,
hello chengejun1984,
could you please also attach them for reference,
thanks
hello jerry
the with and without blank img is uploaded,
hello chengejun1984,
it looks strange,
I assume there’re difference of your signaling, the capture results should not be identical.
could you please have a try to hack the clock as continuous clock for a trial of your v4l2 use-case.
for example,
discontinuous_clk = “no”;
hi jerry
the v4l2 also can’t work,
hello chengejun1984,
may I know what’s the sensor format reported by your v4l2 standard controls.
for example, $ v4l2-ctl -d /dev/video0 --list-formats-ext
hello jerry:
the cmd print as below:
nx@nx-desktop:~$ v4l2-ctl -d /dev/video1 --list-formats-ext
ioctl: VIDIOC_ENUM_FMT
Index : 0
Type : Video Capture
Pixel Format: ‘RG10’
Name : 10-bit Bayer RGRG/GBGB
Size: Discrete 2560x800
Interval: Discrete 0.017s (60.000 fps)
Size: Discrete 1280x800
Interval: Discrete 0.033s (30.000 fps)
nx@nx-desktop:~$
hello chengejun1984,
please narrow down the issue, please check whether this related to sensor modes or not.
for example,
v4l2-ctl -d /dev/video1 --set-fmt-video=width=2560,height=800,pixelformat=RG10 --set-ctrl bypass_mode=0 --stream-mmap --stream-count=100
and
v4l2-ctl -d /dev/video1 --set-fmt-video=width=1280,height=800,pixelformat=RG10 --set-ctrl bypass_mode=0 --stream-mmap --stream-count=100
hello jerry
the second mode width=1280 height=800 's register setting is not set in driver, so this mode is unused, we only the mode0, width=2560 height=800 mode .
hello chengejun1984,
usually, sensor streaming via Argus would be more difficult then v4l2 standard control.
according to those captured images.
are you having bridge device to combine two camera sensor as single CSI input?
could you please also contact with sensor vendor to understand what’s the actual signaling on the CSI port?
it’s would be better if there’s a diagram to elaborate the signal.
thanks
hello jerry
we have a fpga as bridge device to combine two camera sensor as single csi input.
when the fpga not add 110 vblanks, the v4l2-ctl can’t work, after the fpga add 110 vblanks, the v4l2-ctl can work
hello chengejun1984,
is below correct?
there’re two camera sensor output at 1280x800, you have FPGA device to combine both of them as left/right frames.
while you’d add 110 lines, you add 50 lines at top of left camera, 60 lines at bottom of right camera,
hello jerry
yes, at first , the fpga out 2560*800 without 110 vblanking, the v4l2-ctl can’t work, and then we let the fpga vendor add 110 vblanks, the v4l2-ctl can work
hello chengejun1984,
can your bridge device (FPGA) to enable test-pattern-generator?
could you please have a try to ignore dual input camera sources, but output 2560x800 test-pattern frames for v4l2 verification.
thanks
hello jerry:
we have test it, the result is same as the combine frames, when not add vblanks , the v4l2-ctl can’t work, after add vblanks the v4l2-ctl can work.
hello chengejun1984,
please have further more tests with test-pattern-generator.
please narrow down why vblanks matters, you may try to increase/decrease the height of the active region to have verification.
thanks