Can anyone say if the Tegra3 uses an inclusive or exclusive L2 cache? I haven’t been able to find the answer in the ARM PL310 (the L2 cache controller) or Tegra3 technical reference manuals. The ARM PL310 documentation states the L2 can operate in an exclusive mode. Does this mean that it operates in an inclusive mode by default? What modes does the Tegra3 support? What modes are supported by the BIOS (or OS? or firmware?) distributed with the Carma/Kayla platform?
Inclusive Mode: The contents of the L1s are mirrored in the L2.
Exclusive Mode: The cacheline of an address can only appear in one L1 or in the L2, but not both (or another L1). (I think this definition may ignore read-only replicas…)
This doesn’t relate directly to profiler tools, but this seemed to be the best forum to post my question.