Terasic FPGA HDL Incomplete

[phil2]

The Terasic FPGA HDL appears to be very incomplete in the repository and only contains a few top level files. Is there a repository somewhere else that has a file set that is buildable under Quartus Prime Pro to make an FPGA bitstream.

[tlassiter]

The Terasic FPGA HDL in the repo is meant as example code demonstrating how one can instantiate and use the Hololink IP in the Stratix 10 FPGA, not a fully realizable design. Please see Altera’s site for more information as well as link to access the full reference design: Sensor Interfaces for FPGAs