As we know, the Jetson ORIN NX has two I2S interfaces but only one Audio Codec Initiator Clock.
If we want to use two audio devices via I2S0 and I2S1 at the same time, will it work properly?
We are concerned that the single Audio Codec Initiator Clock may only be usable with either I2S0 or I2S1.
Hi,
Generally we would expect single audio codec in hardware design. So in your use-case, you need two audio codecs?
Yes, we may need two audio codecs depends on customer requirement.
Do you have any experience on this hardware configuration?
Hi John7_chen,
Having two audio codec connected separately to I2S0 and I2S1 should be possible.
The Audio codec initiator I believe you referring to AUD_MCLK clock. If so, yes there is only one MCLK clock from Tegra. But this doesn’t be blocker if the Codec supports it’s own PLL generator for clock. May I know what codec you are planning to support.
Yes, we refer to AUD_MCLK clock.
We plan to design I2S0 on I2S Header for external audio device, and I2S1 for audio codec ALC5640.
Do you think it is working?
I need a clarification here,
Does your design involve I2S0 and I2S1 connected to same ALC5640 I2S interfaces or you plan to use two different ALC5640 for each I2S.
Saying so, ALC5640 has internal PLL. if you intend to use we do have support for it in bsp with a different compatible.
Sorry, let me explain more detailed.
We plan to design below on Jetson Orin NX with JP6.2.
I2S0 → leave the I2S Header (let user connect to external audio device by their requirement)
I2S1 → Audio codec ALC5640 on board
Hope these information is clear for you to figure out.
Thank you!
Hi,
Sorry for some delay here.
Got it, Please note RT5640 can work without AUD_MCLK as it has it’s own PLL.
Yes, Tegra support only single AUD_MCLK clock. So if you feel other external codec might need AUD_MCLK, then I2S1 which is connected to ALC5640 shall be used without MCLK.
I hope this clarifies your doubt. Let me know if you need more info here.
Ok, it is clear for my doubt.
Thank for your assistance and help!
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