The can module of spe is abnormal

I use the can module of spe to send and receive messages, and I often encounter the error log of freertos-common/code-common/tegra-can.c:307 [mttcan_tx_complete] “No Tx completion ack received”

Hi easyzoom,

Are you using the devkit or custom board for TX2?
What’s your Jetpack version in use?

Please share the full dmesg for further check.
and also the detailed steps how you configure/setup CAN.

To be precise, I am using TX2-NX ,the software version is R32.7.3,custom board
There is no abnormal printing about mttcan-ivc in dmesg
The can configuration I am using is 1M bitrate

I would like to know the detailed reproduce steps and try to verify on the devkit.
Have you checked if the devkit would hit the same issue? Or the issue only happen on your custom board?

The devkit also has the same problem!

Please help to share the steps how you reproduce on the devkit.

First of all, I want to make sure that the baud rate of can bus communication is “define NBITRATE_PRESCALAR_1M 0x1c09”, is that correct? When I use this value, I cannot perform 1M can bus communication.

I am currently using the code of “define NBITRATE_PRESCALAR_1M 0x0601461d“ and ”writel(2UL, NV_ADDRESS_MAP_CAR_BASE + CLK_RST_CONTROLLER_CLK_SOURCE_CAN1_0);” for can bus communication, I am not sure if the value is accurate

#define NBITRATE_PRESCALAR_500K 0x4409
#define NBITRATE_PRESCALAR_1M   0x1c09
#define DBITRATE_PRESCALAR_2M   0x0d40

How did you get this value?

#define NBITRATE_PRESCALAR_500K 0x4409
#define NBITRATE_PRESCALAR_1M   0x1c09
#define DBITRATE_PRESCALAR_2M   0x0d40

I use the above values, the can bus cannot communicate

I think the clock is not using the pll_aon clock,because the value of readl(NV_ADDRESS_MAP_CAR_BASE + CLK_RST_CONTROLLER_CLK_SOURCE_CAN1_0) is 0xe0000000

I use writel(2UL, NV_ADDRESS_MAP_CAR_BASE + CLK_RST_CONTROLLER_CLK_SOURCE_CAN1_0); to adjust the clock to pll_p clock,“define NBITRATE_PRESCALAR_1M 0x0601461d” is obtained based on the pll_p clock

Could you share the result of the following command?

# cat /sys/kernel/debug/bpmp/debug/clk/can1/parent

Could you refer to the following instruction to verify CAN with 1M?
CAN (Controller Area Network)


So it is using osc rather than pll_aon as source clock.

Do I need to modify the bpmp file to implement the pll_aon clock source?

I implemented pll_aon as source clock by modifying NV_ADDRESS_MAP_CAR_BASE + CLK_RST_CONTROLLER_CLK_SOURCE_CAN1_0 register

I found that ttcan->can_tx_sem in the mttcan_tx_complete function and ttcan->can_tx_sem in the mttcan_tx_cancelled function will affect the transmission efficiency of the can bus.
If I remove ttcan->can_tx_sem in the mttcan_tx_complete function and ttcan->can_tx_sem in the mttcan_tx_cancelled function, the error log “No Tx completion ack received” will appear.

If you want it affective after every boot, please modify it in bpmp dtb.

It seems you are using tegra-can.c rather than mttcan.
Could you also help to verify with mttcan if there’s the similar issue?

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