The csi sparameter has skew between clk and data,does it contain package skew? where can i get csi pacakge delay?
NVCSI only do the deskew at streaming on.
Thanks
we have sent deskew pattern from serdes chip,but the orin deskew bit done status always is 0，how can we debug this problem?tks
What’s the BSP version. Please update the the r35.5 or later release.
Thanks
I have upgraded to 35.6 and the issue is not resolved.
$ sudo busybox devmem 0x15a31cb8
0x00008082
$ cat /etc/nv_tegra_release
R35 (release), REVISION: 6.0, GCID: 37391689, BOARD: t186ref, EABI: aarch64, DATE: Wed Aug 28 09:12:27 UTC 2024
Apply attached RCE firmware to check the log if more information for it.
camera-rtcpu-t234-rce.img.r35.6.dbg (527.3 KB)
[ 451.783092] ar0231 8-0058: camera_power_on 502[DEBUG]DEBUG debug
[ 451.813424] bwmgr API not supported
[ 451.813677] csi5_stream_set_config[DEBUG]: stream_id=4, csi_port=4, is_cphy=0
[ 451.824651] csi5_stream_set_config[DEBUG]: lane_polarity=0x0
[ 451.829959] [RCE] calibration status1 2b2b52d8 status2 275a4e56
[ 451.830473] csi5_stream_set_config[DEBUG]DEBUG debug,csi_lanes=4, cil_settletime=0,cil_config.lp_bypass_mode=1
[ 451.836581] [RCE] calibration status1 28f8d616 status2 1f5b5256
[ 451.846865] csi5_stream_set_config[DEBUG]DEBUG debug, cil_config.mipi_clock_rate=750000
[ 451.847506] ar0231 8-0058: ==lane_rate=0x16 , serdes_pixel_clock = 0x750000000
[ 451.852975] [RCE] calibration status1 20f94290 status2 25085674
[ 451.852977] [RCE] calibration status1 1f39d2f9 status2 2b2936d2
[ 451.861214] ar0231 8-0058: --------cntt= 3-----
[ 451.861217] ar0231 8-0058: camera_set_mode 812[DEBUG]DEBUG debug, s_data->mode=6
[ 451.893234] [RCE] NVCSILP clock rate = 408000000 Hz.
[ 451.953961] [RCE] tegra_nvcsi_stream_set_config(vm0, stream=4, csi=4)
[ 451.960617] [RCE] MIPI clock = 750000 kHz, tHS-SETTLE = 0, tCLK-SETTLE = 0
[ 451.967712] [RCE] ===== NVCSI Stream Configuration =====
[ 451.969954] ar0231 8-0058: camera_start_streaming 828[DEBUG]DEBUG debug, open mipi
[ 451.973197] [RCE] stream_id: PP 4, csi_port: PORT E
[ 451.981479] ar0231 8-0058: Serdes 0x60 w 0x0500 = 0x04
[ 451.985995] [RCE] Brick: PHY 2, Mode: D-PHY
[ 451.985997] [RCE] Partition: CIL A, LP bypass: Enabled, Lanes: 4
[ 451.985998] [RCE] Clock information:
[ 451.985999] [RCE] MIPI clock rate: 750.00 MHz
[ 451.986000] [RCE] T_HS settle: 0, T_CLK settle: 0
[ 451.986001] [RCE] ======================================
[ 451.986003] [RCE] tegra_nvcsi_stream_open(vm0, stream=4, csi=4)
[ 451.991775] ar0231 8-0058: Serdes 0x60 w 0x0900 = 0x04
[ 451.995622] [RCE] nvcsi_reset_data_lanes: NVCSI_PHY_2_NVCSI_CIL_A_SW_RESET_0 = 00000003
[ 452.002286] ar0231 8-0058: Serdes 0x60 w 0x0d00 = 0x04
[ 452.005494] [RCE] nvcsi_reset_data_lanes: NVCSI_PHY_2_NVCSI_CIL_B_SW_RESET_0 = 00000003
[ 452.010473] ar0231 8-0058: Serdes 0x60 w 0x003f = 0x00
[ 452.014832] [RCE] nvcsi_reset_lane_merger: NVCSI_PHY_2_LM_SW_RESET_0 = 00000001
[ 452.014835] [RCE] nvcsi_reset_lane_merger: NVCSI_PHY_2_LM_SW_RESET_0 = 00000000
[ 452.020789] ar0231 8-0058: Serdes 0x60 w 0x0900 = 0x00
[ 452.026410] [RCE] nvcsi_calc_ths_settle ths_settle 53
[ 452.026416] [RCE] nvcsi_calc_ths_settle ths_settle 53
[ 452.032180] ar0231 8-0058: Serdes 0x60 w 0x0500 = 0x00
[ 452.039942] [RCE] nvcsi_calc_ths_settle ths_settle 53
[ 452.039943] [RCE] nvcsi_calc_tclk_settle tclk_settle 75
[ 452.039944] [RCE] nvcsi_reset_data_lanes: NVCSI_PHY_2_NVCSI_CIL_A_SW_RESET_0 = 00000000
[ 452.039945] [RCE] nvcsi_reset_data_lanes: NVCSI_PHY_2_NVCSI_CIL_B_SW_RESET_0 = 00000000
[ 452.045128] tegra-camrtc-capture-vi tegra-capture-vi: corr_err: discarding frame 348, flags: 0, err_data 131072
[ 452.045728] ar0231 8-0058: Serdes 0x60 w 0x0d00 = 0x00
[ 452.078050] tegra-camrtc-capture-vi tegra-capture-vi: corr_err: discarding frame 349, flags: 0, err_data 164
[ 452.093926] [RCE] ISR PHY 2 CIL_A 0xe000000
[ 452.151921] [RCE] ISR PHY 2 CIL_B 0x6000000
[ 452.156241] [RCE] ISR PHY 2 CIL_A 0xe000000
[ 452.160567] [RCE] ISR PHY 2 CIL_B 0x6000000
[ 452.164882] [RCE] ISR PHY 2 CIL_A 0xe000000
[ 452.169204] [RCE] ISR PHY 2 CIL_A 0xe000000
[ 452.173519] [RCE] ISR PHY 2 CIL_B 0x6000000
[ 452.177836] [RCE] ISR PHY 2 CIL_A 0xe000000
[ 452.182148] [RCE] ISR PHY 2 CIL_B 0x6000000
[ 452.186465] [RCE] ISR PHY 2 CIL_A 0xe000000
[ 452.190781] [RCE] ISR PHY 2 CIL_B 0x6000000
[ 452.195105] [RCE] ISR PHY 2 CIL_A 0xe000000
[ 452.199421] [RCE] ISR PHY 2 CIL_A 0xe000000
[ 452.203742] [RCE] ISR PHY 2 CIL_B 0x6000000
[ 452.208063] [RCE] ISR PHY 2 CIL_A 0xe000000
[ 452.212376] [RCE] ISR PHY 2 CIL_B 0x6000000
Make the MIPI clock > 750 Mhz
1 Like
It works,thank you！
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