The difference between TZDRAM and TZRAM

Autonomous Machines Jetson & Embedded Systems Jetson TX2
1

hello,
When I looked up the ATF code, I found that Tegra defines two macros:
1.‘/atf_src/arm-trusted-firmware/plat/nvidia/tegra/include/t186/tegra_def.h’, the file defines the base address and size of TZRAM, the base address is 0x30000000 and the size is 256KB;
2.‘/atf_src/arm-trusted-firmware/plat/nvidia/tegra/include/platform_def.h’, the file defines the size and end address of TZDRAM, the size is 4MB, but the base address of TZDRAM is not given;
May I ask:

  1. What is the difference between TZDRAM and TZRAM? Personally, TZDRAM is an area divided by MC in DRAM (off-chip); TZRAM is an area in on-chip memory.
  2. Where should I find the base address of TZDRAM?

thanks

3

hello fanyangyf688,

it’s bootloader to allocate a dedicated carveout, TZ-DRAM, to run a secure OS.
once a channel is configured as TrustZone, it cannot be used for a non-TrustZone process
please access TX2 Technical Reference Manual,
you may also refer to [19.4.4 TZ Bit Support in Push-Buffer Mechanism] for more details.
thanks

4

hello,
thanks for your reply! but,
I just want to know the specific configuration of TZDRAM in TX2 (such as starting physical address and ending physical address), I don’t know where to find this configuration.
thanks

5

hello fanyangyf688,

the TZ-DRAM base address is included in the aft makefiles,
for example,
$L4T_Sources/r32.4.3/Linux_for_Tegra/source/public/atf_and_trusty/atf/arm-trusted-firmware/plat/nvidia/tegra/soc/t186/platform_t186.mk

# platform settings
TZDRAM_BASE                             := 0x30000000
$(eval $(call add_define,TZDRAM_BASE))

FYI,
this base address of TZ-DRAM were different according to platforms,
it’s 0x40000000; for Jetson Xavier NX, Jetson AGX Xavier series,
it’s 0x30000000; for Jetson TX2 series devices,
it’s 0xff800000; for Jetson Nano, Jetson TX1 series devices,

6

hello,
thanks for your reply!
I also found TZDRAM_BASE, as you said, the value is ‘0x3000_0000’.
But the question is, the memory base address of DRAM is ‘TEGRA_DRAM_BASE=0x8000_0000’, why is TZDRAM_BASE not in the memory range of DRAM?
In addition, ‘TEGRA_TZRAM_BASE=0x3000_0000’, does this mean that both TZDRAM and TZRAM are in the on-chip RAM?
thanks

7

hello fanyangyf688,

please access TX2 Technical Reference Manual, and check Chapter-2.3 for the system address map.
you may also refer to [Table 117: Tegra Carveout Summary] for the details of TZ-DRAM and TZRAM.
thanks

8

thanks,
but I still don’t know where TZDRAM is, I created a new topic, please refer to here.
thanks for your attention.

10

@JerryChang this is a bit off topic, but I am not sure where to point this out.

This actually looks like a bug in how it’s used in the TX2 version of BL3-1 of the ARM-TF:

plat/nvidia/tegra/common/tegra_bl31_setup.c:bl31_check_ns_address()

Because the definition of the symbol TZDRAM_BASE may not be the actual tzdram base address programmed into the memory controller (originally passed by the BPMP’s MB2).

I think for @fanyangyf688’s question, it the address range comes from the BPMP’s boot params, and I think, but I’m not sure, that you can change them because the BL3-1 actually programs the memory controller with the tzdram’s base address and size.

11

hello richard.habeeb,

right, this TZDRAM_BASE variable in the makefile is actually is TZSRAM not the TZDRAM.
please check the follow-up topic, Where is TZDRAM? - #8 by JerryChang,
we have some updates and it’ll include to the next public release (i.e. JetPack-4.6).
thanks