The issue about clock accuracy of CAM0-MCLK

Hi,
I am supporting a camera module on B00 carrier of NANO. My dts about camera mclk as follow:
clocks = <&tegra_car TEGRA210_CLK_CLK_OUT_3>,
<&tegra_car TEGRA210_CLK_CLK_OUT_3_MUX>;
clock-names = “clk_out_3”, “clk_out_3_mux”;
mclk = “clk_out_3”;
clock-frequency = <24000000>;

The result is as follow:

  1. cam0-mclk has 25MHz clock output.
  2. $ sudo cat /sys/kernel/debug/clk/clk_out_3/clk_rate
    24000000
  3. If i adjust the param ‘mclk_khz’ and ‘clock-frequency’ to 23900000, the clock almost is no change. It seems is a fixed value.

My question is as follow:

  1. why has the ‘clk_out_3’ accuracy error? what’s wrong with setting?
  2. What is the corresponding relationship between cam0-mclk and clk_out_3? Is there any documentation for that?

Sorry for the late response, is this still an issue to support? Thanks

It’s generate by it parent and the it divisor scaler is 0.5
You may need to check clock source to calculate the possible clocks.

@kayccc @ShaneCCC Thanks for your reply. The issue has fixed, it was caused by logic analyzer.

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