I am supporting a camera module on B00 carrier of NANO. My dts about camera mclk as follow:
clocks = <&tegra_car TEGRA210_CLK_CLK_OUT_3>,
clock-names = “clk_out_3”, “clk_out_3_mux”;
mclk = “clk_out_3”;
clock-frequency = <24000000>;
The result is as follow:
- cam0-mclk has 25MHz clock output.
- $ sudo cat /sys/kernel/debug/clk/clk_out_3/clk_rate
- If i adjust the param ‘mclk_khz’ and ‘clock-frequency’ to 23900000, the clock almost is no change. It seems is a fixed value.
My question is as follow:
- why has the ‘clk_out_3’ accuracy error? what’s wrong with setting?
- What is the corresponding relationship between cam0-mclk and clk_out_3? Is there any documentation for that?