Why is it introduced in JetSON_AGx_Orin_series_DESIGN_GUIDE_DG-10653-001_V1-6 that PCI Express has UPHY0/1/2, which has 0 to 7 lanes respectively, and shouldn’t there be 24 lanes in total
Not quite sure where you have this number “22”?
Hi
It is mentioned in documents Jetson_AGX_Orin_Series_Data_Sheet_DS-10662-001_v1.5 and Jetson_AGX_Orin_Series_Design_Guide_DG-10653-001_v1.6。
Hi,
Because not every lane could be used as PCIe. The overall UPHY lanes are shared by USBSS/PCIe/MGBE.
Thus, not 24.
Hi,
You went into the wrong direction.
Please do not rely on TRM document. We only support fixed pattern as mentioned on design guide…
For example, C2 and C3 are totally not existing on any Orin jetson platform…
請你參考design guide設計…不要看TRM.
Copy that. Thank you.
hi Wayne
I also want to ask you about the pcie configuration。
According to the above picture, each PCIE port supports Root port mode. Can C4 ports (lan4-lan7 of UPHY0) be divided into four x1 ports to connect to four x1 devices? If you have a C4controller, does that work?
No, as I already told. You can only follow the available configuration mentioned on the design guide.
hello wayne
Can I ask which types of PHY chips are supported by the RGMII interface on the AGX orin module, and which types of NIC drivers have been adapted?
Please file a new topic if your question is not related to original one.
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