The P2U (pipe2uphy) phandle does not exist in current BSP source (R39.2.1)

Robotics & Edge Computing Jetson Systems Jetson Orin Nano
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1

Hi,

I’m following the “Enabling PCIe in a Customer Carrier Board Design” section here:

Step 4 says:

“Add the P2U (pipe2uphy) phandle entries as a phy property in the PCIe controller DT node. The P2U nodes for PCIe are defined in the SoC PCIe DTSI: $(TOP)/hardware/nvidia/soc/t23x/kernel-dts/tegra234-soc/tegra234-soc-pcie.dtsi. Each P2U node is a 1:1 map to the UPHY lanes.”

However, tegra234-soc-pcie.dtsi does not exist anywhere in my extracted BSP source tree, and neither does pipe2uphy:

jetson-docker@desktop:~/bsp/kernel_src/Linux_for_Tegra/source/hardware$ find . -iname "tegra234-soc-pcie.dtsi"
jetson-docker@desktop:~/bsp/kernel_src/Linux_for_Tegra/source/hardware$
jetson-docker@desktop:~/bsp/kernel_src/Linux_for_Tegra/source/hardware$ grep -rn "pipe2uphy" .
jetson-docker@desktop:~/bsp/kernel_src/Linux_for_Tegra/source/hardware$

Environment:

  • JetPack / Jetson Linux: R39.2.1
  • Module: Jetson Orin Nano (planning to move to Jetson Orin NX soon, which uses the same doc page / SoC, so this affects both)
  • BSP source obtained via Driver Package (BSP) Sources

I found an older forum thread ( Can't find files in their paths ) where this same issue was reported back on R36.3, and NVIDIA staff confirmed the file had moved:

“the soc-pcie.dtsi is now as hardware/nvidia/t23x/nv-public/tegra234.dtsi”

I can confirm that path(tegra234.dtsi) also doesn’t seem to define a pipe2uphy/P2U node in the R39.2.1 tree, so I’m not sure it’s still accurate either.

Could someone confirm:

  1. Where the P2U (pipe2uphy) nodes are actually defined in the current (R39.2.1) BSP source? I can’t reference the correct phy phandle for a custom carrier board PCIe port.
  2. Is the document going to be updated to reflect the current file path? This same broken reference has apparently persisted since at least R36.3.

Thanks in advance.

Regards,

Jung.

3

Which PCIe are you trying to enable here?

4

C1 (x1, Wi-Fi/BT) and C4 (x4, NVMe M.2 Key M) match the default devkit configuration. The one that’s new for our custom carrier board is C7 (x2, for a 5G module), which requires switching UPHY config to gbe-uphy-config-8 — this is the controller I need the correct P2U phandle reference for.

  • C1(x1): Wi-Fi BT Module
  • C4(x4): NVMe SSD(M.2 M-Key)
  • C7(x2): 5G Module
5

No need to do that. PCIe C7 is also enabled on Orin Nano devkit by default.

6

Got it, thanks. Since C7 is already enabled by default, could you point me to which combined DTS file (e.g. tegra234-p3767-0000+p3768-0000.dts or similar) has the C7 node with its existing phy/P2U mapping? I’d like to reference that directly for our custom carrier board’s C7 routing.

7

p2u is defined in tegra234.dtsi.

Which PCIe controller to use which p2u is defined in tegra234-p3768-0000+p3767.dtsi for Orin NX/Nano.

For example,

201                 /* C7 - M.2 Key-M */
202                 pcie@141e0000 {
203                         status = "okay";
204 
205                         vddio-pex-ctl-supply = <&vdd_1v8_ao>;
206 
207                         phys = <&p2u_gbe_0>, <&p2u_gbe_1>;
208                         phy-names = "p2u-0", "p2u-1";
209                 };