I check the documents of xavier.
There is 8 (2 lanes csi) ,they are A -B-C-D -E - F -G -H.
We plan use 2 chips of FD-LINK III DS90UB960.
But we did not sure our design is right or not .
the nvidia official eg is below:
We have two design of the 4 4-lanes
- Which plan is right ? or they are all reasonable ?
Please help me have a check.