# \[Thor\]SW Shutdown Case & Reset **URL:** \ **Category:** Jetson Thor\ **Tags:** board-design\ **Created:** [November 9, 2026, 10:34am UTC](https://forums.developer.nvidia.com/t/thor-sw-shutdown-case-reset/388550 "2026-11-09T10:34:31Z")\ **Posts on this page:** 6\ **Page:** 1
**Author:** ![rain1\_wang](https://developer.download.nvidia.com/images/forums/profile-default-devtalk-84.png) [@rain1\_wang](https://forums.developer.nvidia.com/u/rain1_wang)\ **Post date:** [November 9, 2026, 10:34am UTC](https://forums.developer.nvidia.com/t/thor-sw-shutdown-case-reset/388550/1 "2026-11-09T10:34:31Z")
Hi Nvidia We have referenced the Design Guide to design the timing for SW Shutdown using the MCU. Please help verify if it is correct. The VDD\_3V3/VDD\_1V8 Power Good signal is controlled by CARRIER\_POWER\_ON. ![image](https://global.discourse-cdn.com/nvidia/original/4X/9/0/b/90b17c9c7d0213bf3c1b88e08a65c6e1facedc54.png) ---
**Author:** ![rain1\_wang](https://developer.download.nvidia.com/images/forums/profile-default-devtalk-84.png) [@rain1\_wang](https://forums.developer.nvidia.com/u/rain1_wang)\ **Post date:** [November 9, 2026, 10:35am UTC](https://forums.developer.nvidia.com/t/thor-sw-shutdown-case-reset/388550/2 "2026-11-09T10:35:45Z")
![image](https://global.discourse-cdn.com/nvidia/original/4X/c/d/a/cda10465beb0e851b22488b4bb2f6a2a7aed150b.png) ---
**Author:** ![EricGggg](https://sea2.discourse-cdn.com/nvidia/user_avatar/forums.developer.nvidia.com/ericgggg/32/382649_2.png) [@EricGggg](https://forums.developer.nvidia.com/u/EricGggg)\ **Post date:** [November 9, 2026, 7:10pm UTC](https://forums.developer.nvidia.com/t/thor-sw-shutdown-case-reset/388550/6 "2026-11-09T19:10:24Z")
Unfortunately, we are not able to review or verify individual custom carrier board designs, including timing diagrams, on the forum. Please check your design against the SW shutdown sequence and timing requirements in the _Jetson Thor Series Modules Design Guide_. The Schematic Checklist in the Design Guide and the Jetson AGX Thor Developer Kit carrier board (P4071) schematics are also useful references. If something in the Design Guide is unclear, such as a specific timing parameter or a signal requirement, please let us know which part, and we will be happy to help clarify it. If you see an actual problem on your board, such as an unexpected reset during SW shutdown, please share the measured waveforms (for example SHUTDOWN\_REQ\*, POWER\_EN, SYS\_RESET\*, and CARRIER\_POWER\_ON) along with a short description. We can then look into it further. ---
**Author:** ![rain1\_wang](https://developer.download.nvidia.com/images/forums/profile-default-devtalk-84.png) [@rain1\_wang](https://forums.developer.nvidia.com/u/rain1_wang)\ **Post date:** [November 10, 2026, 1:22am UTC](https://forums.developer.nvidia.com/t/thor-sw-shutdown-case-reset/388550/7 "2026-11-10T01:22:14Z")
Our question is about a possible conflict between the SW shutdown timing and the HW reset timing. The first step in the SW shutdown sequence is Sys\_Reset\_N being pulled low — but that is also the trigger condition for a HW reset. As a result, we are seeing the MCU stuck in the SW shutdown sequence after a HW reset, waiting for Carrier\_Power\_ON to be pulled low. Since this is a reset sequence, Carrier\_Power\_ON never gets pulled low. How does NVIDIA prevent this on your side? ---
**Author:** ![rain1\_wang](https://developer.download.nvidia.com/images/forums/profile-default-devtalk-84.png) [@rain1\_wang](https://forums.developer.nvidia.com/u/rain1_wang)\ **Post date:** [November 13, 2026, 8:57am UTC](https://forums.developer.nvidia.com/t/thor-sw-shutdown-case-reset/388550/10 "2026-11-13T08:57:37Z")
Hi Eric Any update？ ---
**Author:** ![EricGggg](https://sea2.discourse-cdn.com/nvidia/user_avatar/forums.developer.nvidia.com/ericgggg/32/382649_2.png) [@EricGggg](https://forums.developer.nvidia.com/u/EricGggg)\ **Post date:** [November 14, 2026, 12:31am UTC](https://forums.developer.nvidia.com/t/thor-sw-shutdown-case-reset/388550/11 "2026-11-14T00:31:59Z")
n the NVIDIA reference design, SYS\_RESET\_N is not used as the trigger to start the SW shutdown sequence. The carrier board power control logic (the Button MCU on the DevKit) uses **CARRIER\_POWER\_ON** to decide when to power down. - **HW reset (reset button press):** SYS\_RESET\_N goes low and only the module is reset. The power sequence does not change, so **CARRIER\_POWER\_ON stays high** during the reset. - **SW shutdown:** The module drives **CARRIER\_POWER\_ON low**. The carrier board logic detects this and starts the power-down sequence. - SYS\_RESET\_N also goes low when a reset begins. To avoid treating short transitions during a reset as a shutdown, the reference MCU ignores CARRIER\_POWER\_ON for a short time after SYS\_RESET\_N goes low. After that time, if CARRIER\_POWER\_ON is low, it continues with the shutdown. **Recommendation:** Please update your MCU logic so that it starts the shutdown sequence when **CARRIER\_POWER\_ON goes low** , not when SYS\_RESET\_N goes low. With this change, a HW reset will not be detected as a SW shutdown, and your MCU will not get stuck waiting for CARRIER\_POWER\_ON to go low. For the timing requirements, please refer to the power-down (shutdown) sequence in the Jetson Thor Series Modules Design Guide.