Timestamping GPIO transaction with SPE GTE

[andrea.pascolini]

Hello, we have been using SPE processor to timestamp events happening at GPIO DD0 (pin 187) in Xavier NX, configuring tegra_gte_id_aon to handle NV_AON_GTE_SLICE2_IRQ_GPIO_14 events as follows:

tegra_gte_slice_set_enable_mask(&tegra_gte_id_aon, 2, BIT(NV_AON_GTE_SLICE2_IRQ_GPIO_14));

This is working pretty well, and now we would like to add a second GPIO line to be timestamped. How could we get to know the mapping between GTE slice IRQ IDs as listed in l4t-rt/freertos-common-t19x/include-soc/t194-aon/gte-tegra-hw.h (example: NV_AON_GTE_SLICE2_IRQ_GPIO_14) and Xavier NX physical GPIO lines (example: DD0)? We have not been able to find this information either in SPE SDK or in Xavier TRM

Many thanks

Andrea

[jachen]

Hello, Andrea:
Please list available GPIO pins you may use.

br
ChenJian

[andrea.pascolini]

Hi Jachen, here three possible candidates, from Xavier NX pinout:

• p193 / T06
• p195 / T07
• p197 / U00

Thanks

Andrea

[jachen]

Hello, Andrea:
The three pins you listed are not in AON cluster, and they cannot be accessed from SPE firmware.
GPIO T 06
GPIO T 07
GPIO U 00
Please change your design. Refer to “l4t-rt/freertos-common-t19x/include-soc/t194/tegra194-gpio-hw.h” for GPIOs in AON cluster.

br
Chenjian

[andrea.pascolini]

Hi Jachen,

ok, so three AON pins:

p130 CC.03
p218 CC.04
p185 CC.07

Thanks

Andrea

[jachen]

Hello, Andrea:
Try this, and let me know if it can work, or not.

#define NV_AON_GTE_SLICE2_IRQ_GPIO_19 19 /*  cc[03], */
#define NV_AON_GTE_SLICE2_IRQ_GPIO_18 18 /*  cc[04], */
#define NV_AON_GTE_SLICE2_IRQ_GPIO_15 15 /*  cc[07], */

br
Chenjian

[andrea.pascolini]

Hi Jachen,

testing them will take us some time, I have no other questions about this topic for now, thanks for the support

Andrea