Timing between CARRIER_POWER_ON and SYS_RESET_N

Hi

Based on the power up sequence diagram from OEM doc, there is a gap in time between CARRIER_POWER_ON and SYS_RESET_N:

In my understanding both CARRIER_POWER_ON and SYS_RESET_N are driven by Xavier during power up, correct? Xavier SoM first drive CARRIER_POWER_ON high in order to turn on 3.3V and 1.8V on carrier. Then, Xavier will release SYS_RESET_N in order to let SoC boot up, correct?

But what is the exact timing gap between CARRIER_POWER_ON and SYS_RESET_N? I couldn’t find it in OEM doc (or any other doc).

In the same chapter in OEM doc, there is another similar timing sequence diagram:

It listed some timing characteristics, but not including the one (between CARRIER_POWER_ON and SYS_RESET_N) that I am looking for.

Regards.

Yes as your understanding. No strict timing on it, in general you can take dozens of milliseconds as reference from carrier_power_on to sys_reset_n, and it is carrier board design dependent.

Hi,

Thanks for your reply.

As documented in OEM doc, SYS_RESET_N is a bi-direction open-drain 1.8V pin. So, either PMIC on Xavier Module, or MCU on carrier can drive it low. Correct? (Similar to I2C signal lines.)

I should mention that I am designing my own carrier board with an STM32 as MCU running my own firmware on it. (instead of using EFM8SB10F8G-A-QFN20). So, I have full control on how MCU behave.

  1. Will PMIC on Xavier Module keep holding SYS_RESET_N low during the power up sequence, until after CARRIER_POWER_ON is driven high? Then, after CARRIER_POWER_ON is driven high, PMIC will release SYS_RESET_N which will cause it to be pull up to 1.8V. (Then, SoC will boot afterward.)

  2. If “1” is correct, do you have a time estimate on the delay/gap between CARRIER_POWER_ON and SYS_RESET_N? Note that in this case, PMIC on Module is the only one controls SYS_RESET_N. So, when PMIC releases SYS_RESET_N is totally depending on how PMIC behaves.

  3. I think in my MCU (STM32) firmware, I can optionally driving SYS_RESET_N low during the power up sequence. After CARRIER_POWER_ON is driven high, my MCU firmware can add any delay that I want before releasing SYS_RESET_N. In this case, the delay/gap time between CARRIER_POWER_ON and SYS_RESET_N is under my own control. Correct?

Can you please confirm all my questions 1, 2, 3?

Regards.

Yes, PMIC will hold RESET during power up. The timing after CARRIER_POWER_ON is about 40ms in theory if it is not affected by carrier board. But also this timing is programmable (OTP), it can be 1.28ms ~ 81.92ms. You can check that manually for precise timing on your design.

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Hi,

Thanks so much for your confirmation and info.

Where can I find the document for that OTP? Can you please provide me the link?
Is it the OTP in PMIC? Or OTP in tegra SoC? (I think it should be the OTP of PMIC.)

Regards.

The PMIC is MAX20024, please check with vendor for datasheet.