The Design Guide timing diagram is very clear on the timing/logic between MODULE_POWER_ON (input) and CARRIER_POWER_ON (output), till I came across a note, which may prompt to be an ERROR or typo to me. Please clarify:
The note on D.G V1.2 Page 22, “The design should de-assert (low) MODULE_POWER_ON if VDDIN_PWR_BAD_N is asserted (low), CARRIER_POWER_ON is de-asserted (low), or MODULE_SHDN_N is asserted (low).”
The issue is on the critical output CARRIER_POWER_ON only. If we implement a gate logic to assert MODULE_POWER_ON low, when CARRIER_POWER_ON = 0, the module would be locked up in a power-off state, because MODULE_POWER_ON would never get a chance to be driven high. The note puts the input/output logic in a dead-loop.
As you can see in the note in page 20: Note: If the main power rails (SYS_VIN_HV/MV) are not powered off, it is possible for the system to power on again depending on the state of the signals. If the system was powered down due to a shutdown condition that is cleared, the system may power back on. Unless this is desired, a means of keeping the module powered off should be provided. One way is to latch the state of CARRIER_POWER_ON when it goes from high to low (module powered off) and using this to keep MODULE_POWER_ON inactive (low).
Yes, I am aware of this note and it has been well-understood. I have no problem with this note (as you posted above). With your emphasis, I believe it means we should ignore CARRIER_POWER_ON before power-up, only latch it when it transits from High–Low falling edge, to prevent automatic power-on.
Thanks for the reply. I have no more question on this topic. It can be closed. You support is much appreciated.
