# TIMING SPEC FOR PCIE 16X INTERFACE **URL:** \ **Category:** Jetson AGX Orin\ **Tags:** hw, level3, board-design\ **Created:** [April 26, 2025, 4:09pm UTC](https://forums.developer.nvidia.com/t/timing-spec-for-pcie-16x-interface/331575 "2025-04-26T16:09:53Z")\ **Posts on this page:** 8\ **Page:** 1
**Author:** ![liubh5701023](https://developer.download.nvidia.com/images/forums/profile-default-devtalk-84.png) [@liubh5701023](https://forums.developer.nvidia.com/u/liubh5701023)\ **Post date:** [April 26, 2025, 4:09pm UTC](https://forums.developer.nvidia.com/t/timing-spec-for-pcie-16x-interface/331575/1 "2025-04-26T16:09:53Z")
Is there a timing spec for the PCIe 8x slot relative signals: SOC controls these signals. PCIE\_12V\_EN\_N module pin A59 GPIO05 PCIE\_3V3\_EN module pin L48 UART4\_RX PCIE5\_CLKREQ\_N module pin C8 PEX\_L5\_CLKREQ\_N PCIE5\_RST\_N module pin H10 PEX\_L5\_RST\_N ---
**Author:** ![liubh5701023](https://developer.download.nvidia.com/images/forums/profile-default-devtalk-84.png) [@liubh5701023](https://forums.developer.nvidia.com/u/liubh5701023)\ **Post date:** [April 30, 2025, 5:00am UTC](https://forums.developer.nvidia.com/t/timing-spec-for-pcie-16x-interface/331575/3 "2025-04-30T05:00:48Z")
Update: For the CLK\_req usage, is this pin necessary? The retimer supplier suggests the clock can freely run to the retimer, with no clk req control. Is this suggestion workable? Another question is that the initial time for the retimer is 2s, so the PCI reset should assert later 2s after the power is valid to the retimer chip? Is there a suggestion for the 2s delay to reset the retimer chip? ---
**Author:** ![sgursal](https://sea2.discourse-cdn.com/nvidia/user_avatar/forums.developer.nvidia.com/sgursal/32/394208_2.png) [@sgursal](https://forums.developer.nvidia.com/u/sgursal)\ **Post date:** [April 30, 2025, 3:48pm UTC](https://forums.developer.nvidia.com/t/timing-spec-for-pcie-16x-interface/331575/4 "2025-04-30T15:48:29Z")
Please refer to PCIe CEM Specification and PCIe Base Specification. With Common Clock architecture, CLKREQ\_N is Optional. EMI issues will be reduced if clocks to open PCIe connectors are turned off at the clock source. ---
**Author:** ![sgursal](https://sea2.discourse-cdn.com/nvidia/user_avatar/forums.developer.nvidia.com/sgursal/32/394208_2.png) [@sgursal](https://forums.developer.nvidia.com/u/sgursal)\ **Post date:** [April 30, 2025, 3:55pm UTC](https://forums.developer.nvidia.com/t/timing-spec-for-pcie-16x-interface/331575/5 "2025-04-30T15:55:21Z")
We do not have timing spec for PCIe x8 slot. These parameters are system design dependent like choice of voltage regulators, voltage ramp up and stabilization time. Please refer to PCIe CEM specification for further guidance on relative timing for Power Up. ---
**Author:** ![liubh5701023](https://developer.download.nvidia.com/images/forums/profile-default-devtalk-84.png) [@liubh5701023](https://forums.developer.nvidia.com/u/liubh5701023)\ **Post date:** [May 11, 2025, 12:43am UTC](https://forums.developer.nvidia.com/t/timing-spec-for-pcie-16x-interface/331575/7 "2025-05-11T00:43:45Z")
From the timing spec: the reset\_n is about 200ms from the first power rail on to the soc reset, but the pcie reset signal is from SOC, and pcie power rail is controlled by the pcie\_3v3\_EN and PCIE\_12V\_En\_N, where can I adjust the timing for these 3 signals? ![image](https://global.discourse-cdn.com/nvidia/original/4X/d/8/0/d8084b45fc0061e86d54446cb74ebe50d7ca027d.png) ---
**Author:** ![WayneWWW](https://sea2.discourse-cdn.com/nvidia/user_avatar/forums.developer.nvidia.com/waynewww/32/14043_2.png) [@WayneWWW](https://forums.developer.nvidia.com/u/WayneWWW)\ **Post date:** [May 16, 2025, 9:53am UTC](https://forums.developer.nvidia.com/t/timing-spec-for-pcie-16x-interface/331575/9 "2025-05-16T09:53:25Z")
To adjust PCIE\_3V3\_EN, you could check pcie-tegra194.c and function tegra\_pcie\_enable\_slot\_regulators and tegra\_pcie\_dw\_probe for process of pcie init. ---
**Author:** ![sgursal](https://sea2.discourse-cdn.com/nvidia/user_avatar/forums.developer.nvidia.com/sgursal/32/394208_2.png) [@sgursal](https://forums.developer.nvidia.com/u/sgursal)\ **Post date:** [May 19, 2025, 5:39pm UTC](https://forums.developer.nvidia.com/t/timing-spec-for-pcie-16x-interface/331575/10 "2025-05-19T17:39:28Z")
Also, refer to [Jetson AGX Orin Platform Adaptation and Bring-Up — NVIDIA Jetson Linux Developer Guide](https://docs.nvidia.com/jetson/archives/r36.4.3/DeveloperGuide/HR/JetsonModuleAdaptationAndBringUp/JetsonAgxOrinSeries.html#enable-pcie-in-a-customer-cvb-design) ![image](https://global.discourse-cdn.com/nvidia/original/4X/3/e/e/3eefd2164ef9ff4e75494e1c908472ad6b510d3e.png) ---
**Author:** ![system](https://sea2.discourse-cdn.com/nvidia/user_avatar/forums.developer.nvidia.com/system/32/68080_2.png) [@system](https://forums.developer.nvidia.com/u/system)\ **Post date:** [June 2, 2025, 5:39pm UTC](https://forums.developer.nvidia.com/t/timing-spec-for-pcie-16x-interface/331575/11 "2025-06-02T17:39:41Z")
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