Timing spec for system reset and pcie reset

[liubh5701023]

Is there the timing spec for the L60 SYS_RST_IN_N and PCIE reset for each controller?

[sgursal]

Please refer to the Jetson AGX Orin Series Design Guide for relative timing of power on sequence. SYS_RESET_N is driven by the power sequencer on the module during power-on. It does not need to be controlled by the carrier board. If the carrier board supplies required for powering on require additional time, the PERIPHERAL_RESET_N signal can be held low. This will keep the SoC and other boot devices in reset.

For PCIe reset timing refer to the PCIe specification.

[liubh5701023]

SYS_RESET_N is from SOC, but the PCIe reset is from SOC., is there a timing spec for both signals?

[sgursal]

There is no timing spec between SYS_RESET_N and PEX_x_RST_N. Root Port (RP) does have power gating. RP is power gated until it sees End Point (EP) present, or RP can be set to be always up. How and when reset is asserted depends on which side is up first. If EP is up first, RP won’t send reset to EP. If RP up first than EP, RP detects present pin and sends out reset to EP. RP itself is out of power gaiting and it is all software (PCIe SW stack) controlled.