Timming of Toshiba TC358743 driver

   Hello,I want to  capture HDMI signal(1600x1200@60fps) using my custom board through tc358743XBG.I had tested and captured  the 1080p@60fps video successfully. According to standard timing data and my source device timing out, I  have setted the EDID, but the UXGA(1600x1200@60fps) resolution always does'nt work.

EDID message:
test1 pclk=161,hs=168,hbp=280,h_act=1600,hfp=112,vs=4,vbp=28,v_act=1200,vfp=3
or
test2 pclk=162,hs=64,hbp=192,h_act=1600,hfp=304,vs=3,vbp=46,v_act=1200,vfp=1

jetpack:4.3 kernel:4.9.140

There is some debug message:

nvidia@nvidia-desktop:~$ v4l2-ctl --log-status

Status Log:

[ 75.562090] tegra-vi4 15700000.vi: ================= START STATUS =================
[ 75.562617] tc358743 2-000f: -----Chip status-----
[ 75.562842] tc358743 2-000f: Chip ID: 0x00
[ 75.563033] tc358743 2-000f: Chip revision: 0x00
[ 75.563037] tc358743 2-000f: Reset: IR: 1, CEC: 1, CSI TX: 0, HDMI: 0
[ 75.563039] tc358743 2-000f: Sleep mode: off
[ 75.563041] tc358743 2-000f: Cable detected (+5V power): yes
[ 75.563204] tc358743 2-000f: DDC lines enabled: yes
[ 75.563367] tc358743 2-000f: Hotplug enabled: yes
[ 75.563554] tc358743 2-000f: CEC enabled: no
[ 75.563555] tc358743 2-000f: -----Signal status-----
[ 75.563557] tc358743 2-000f: TMDS signal detected: no
[ 75.563559] tc358743 2-000f: Stable sync signal: no
[ 75.563561] tc358743 2-000f: PHY PLL locked: no
[ 75.563562] tc358743 2-000f: PHY DE detected: yes
[ 75.563728] tc358743 2-000f: tc358743_get_detected_timings: no valid signal
[ 75.563730] tc358743 2-000f: No video detected
[ 75.563735] tc358743 2-000f: Configured format: 1600x1200p59.86 (2160x1245)
[ 75.563737] tc358743 2-000f: horizontal: fp = 112, +sync = 168, bp = 280
[ 75.563740] tc358743 2-000f: vertical: fp = 3, +sync = 4, bp = 38
[ 75.563742] tc358743 2-000f: pixelclock: 161000000
[ 75.563745] tc358743 2-000f: flags (0x0):
[ 75.563747] tc358743 2-000f: standards (0x6): DMT CVT
[ 75.563748] tc358743 2-000f: -----CSI-TX status-----
[ 75.563751] tc358743 2-000f: Lanes needed: 4
[ 75.563988] tc358743 2-000f: Lanes in use: 4
[ 75.564174] tc358743 2-000f: Waiting for particular sync signal: no
[ 75.564360] tc358743 2-000f: Transmit mode: no
[ 75.564548] tc358743 2-000f: Receive mode: no
[ 75.564736] tc358743 2-000f: Stopped: no
[ 75.564737] tc358743 2-000f: Color space: YCbCr 422 16-bit
[ 75.564900] tc358743 2-000f: -----DVI-D status-----
[ 75.564902] tc358743 2-000f: HDCP encrypted content: no
[ 75.564906] tc358743 2-000f: Input color space: RGB full range
[ 75.565072] tegra-vi4 15700000.vi: ================== END STATUS ==================

nvidia@nvidia-desktop:~$ dmesg | grep tc3
[ 72.038794] tc358743: no symbol version for module_layout
[ 72.044236] tc358743: loading out-of-tree module taints kernel.
[ 72.051320] tc358743 2-000f: 1-chip found @ 0xf (3180000.i2c)
[ 72.085976] tc358743 2-000f: 2-Subdev init done
[ 72.086665] tc358743 2-000f: 3-ctrl handler init done
[ 72.086914] tc358743 2-000f: 4-tc358743_ctrl_audio_sampling_rate 0
[ 72.087138] tc358743 2-000f: 5-tc358743_ctrl_audio_present no
[ 72.087150] tc358743 2-000f: A bunch of new cutoms done
[ 72.087775] tc358743 2-000f: 6-Controls updated
[ 72.088193] tc358743 2-000f: 7-Work queue created
[ 72.088200] tc358743 2-000f: 8-About to call tegra_media_entity_init
[ 72.088208] tc358743 2-000f: 9-tegra_media_entity_init complete
[ 72.088215] tc358743 2-000f: 10-About to register subdev
[ 72.088248] tegra-vi4 15700000.vi: subdev tc358743 2-000f bound
[ 72.090441] tc358743 2-000f: 11-Register subdev complete: 0
[ 72.090445] tc358743 2-000f: 12-before tc358743_initial_setup
[ 72.090446] tc358743 2-000f: tc358743_initial_setup:enter into this
[ 72.090959] tc358743 2-000f: tc358743_reset:
[ 72.091258] tc358743 2-000f: tc358743_sleep_mode(): disable
[ 72.095319] tc358743 2-000f: **********DDC CONTROL: 0x32
[ 72.095479] tc358743 2-000f: **********HPD CONTROL: 0x0
[ 72.095482] tc358743 2-000f: tc358743_set_hdmi_phy:enter into this
[ 72.097406] tc358743 2-000f: tc358743_set_hdmi_phy:Exit
[ 72.099099] tc358743 2-000f: tc358743_set_hdmi_audio:enter into this
[ 72.100970] tc358743 2-000f: tc358743_set_hdmi_info_frame_mode:enter into this
[ 72.102477] tc358743 2-000f: tc358743_initial_setup:Exit
[ 72.102480] tc358743 2-000f: 13-after tc358743_initial_setup
[ 72.102483] tc358743 2-000f: 14-before tc358743_s_dv_timings
[ 72.102486] tc358743 2-000f: enable_stream: disable
[ 72.103290] tc358743 2-000f: tc358743_set_pll:
[ 72.103293] tc358743 2-000f: tc358743_set_pll: updating PLL clock
[ 72.103295] tc358743 2-000f: tc358743_sleep_mode(): enable
[ 72.104414] tc358743 2-000f: tc358743_sleep_mode(): disable
[ 72.104738] tc358743 2-000f: tc358743_set_csi:enter into this
[ 72.104916] tc358743 2-000f: tc358743_reset:
[ 72.108491] tc358743 2-000f: tc358743_set_csi:Exit
[ 72.108495] tc358743 2-000f: 15-after tc358743_s_dv_timings
[ 72.108499] tc358743 2-000f: tc358743_set_csi_color_space: YCbCr 422 16-bit
[ 72.109370] tc358743 2-000f: 16-before tc358743_init_interrupts, irq: 242
[ 72.111127] tc358743 2-000f: 17-after tc358743_init_interrupts, irq: 242
[ 72.111406] tc358743 2-000f: tc358743_enable_interrupts: cable connected = 0
[ 72.112170] tc358743 2-000f: tc358743 found @ 0xf (3180000.i2c)
[ 72.112174] tc358743 2-000f: tc358743_s_edid, pad 0, start block 0, blocks 2
[ 72.112176] tc358743 2-000f: tc358743_disable_edid:
[ 72.119226] tc358743 2-000f: tc358743_s_edid is completed
[ 72.119232] tc358743 2-000f: tc358743_g_edid is working!
[ 72.125684] tc358743 2-000f: **********0x8c36: 0xe4
[ 72.125841] tc358743 2-000f: **********0x8c37: 0x3e
[ 72.126002] tc358743 2-000f: **********0x8c38: 0x40
[ 72.126182] tc358743 2-000f: **********39: 0x30
[ 72.126352] tc358743 2-000f: **********3A: 0x62
[ 72.126510] tc358743 2-000f: **********3B: 0xb0
[ 72.126665] tc358743 2-000f: **********3C: 0x2d
[ 72.126819] tc358743 2-000f: **********3D: 0x40
[ 72.126974] tc358743 2-000f: **********3E: 0x70
[ 72.127129] tc358743 2-000f: **********3F: 0xa8
[ 72.127285] tc358743 2-000f: **********40: 0x34
[ 72.127449] tc358743 2-000f: **********41: 0x0
[ 72.127453] tc358743 2-000f: Probe complete
[ 72.191866] tc358743 2-000f: tc358743_isr: IntStatus = 0x0200
[ 72.192789] tc358743 2-000f: tc358743_hdmi_sys_int_handler: SYS_INT =0x01
[ 72.192993] tc358743 2-000f: tc358743_hdmi_sys_int_handler: Tx 5V power present: yes
[ 72.193006] tc358743 2-000f: tc358743_enable_edid is working!:
[ 72.193029] tc358743 2-000f: tc358743_enable_interrupts: cable connected = 1
[ 72.294035] tc358743 2-000f: tc358743_delayed_work_enable_hotplug is workin:
[ 75.562617] tc358743 2-000f: -----Chip status-----
[ 75.562842] tc358743 2-000f: Chip ID: 0x00
[ 75.563033] tc358743 2-000f: Chip revision: 0x00
[ 75.563037] tc358743 2-000f: Reset: IR: 1, CEC: 1, CSI TX: 0, HDMI: 0
[ 75.563039] tc358743 2-000f: Sleep mode: off
[ 75.563041] tc358743 2-000f: Cable detected (+5V power): yes
[ 75.563204] tc358743 2-000f: DDC lines enabled: yes
[ 75.563367] tc358743 2-000f: Hotplug enabled: yes
[ 75.563554] tc358743 2-000f: CEC enabled: no
[ 75.563555] tc358743 2-000f: -----Signal status-----
[ 75.563557] tc358743 2-000f: TMDS signal detected: no
[ 75.563559] tc358743 2-000f: Stable sync signal: no
[ 75.563561] tc358743 2-000f: PHY PLL locked: no
[ 75.563562] tc358743 2-000f: PHY DE detected: yes
[ 75.563728] tc358743 2-000f: tc358743_get_detected_timings: no valid signal
[ 75.563730] tc358743 2-000f: No video detected
[ 75.563735] tc358743 2-000f: Configured format: 1600x1200p59.86 (2160x1245)
[ 75.563737] tc358743 2-000f: horizontal: fp = 112, +sync = 168, bp = 280
[ 75.563740] tc358743 2-000f: vertical: fp = 3, +sync = 4, bp = 38
[ 75.563742] tc358743 2-000f: pixelclock: 161000000
[ 75.563745] tc358743 2-000f: flags (0x0):
[ 75.563747] tc358743 2-000f: standards (0x6): DMT CVT
[ 75.563748] tc358743 2-000f: -----CSI-TX status-----
[ 75.563751] tc358743 2-000f: Lanes needed: 4
[ 75.563988] tc358743 2-000f: Lanes in use: 4
[ 75.564174] tc358743 2-000f: Waiting for particular sync signal: no
[ 75.564360] tc358743 2-000f: Transmit mode: no
[ 75.564548] tc358743 2-000f: Receive mode: no
[ 75.564736] tc358743 2-000f: Stopped: no
[ 75.564737] tc358743 2-000f: Color space: YCbCr 422 16-bit
[ 75.564900] tc358743 2-000f: -----DVI-D status-----
[ 75.564902] tc358743 2-000f: HDCP encrypted content: no
[ 75.564906] tc358743 2-000f: Input color space: RGB full range

Sometimes I can get the 1600x1200@60fps timing successfully,but sometimes not,why?

hello Bit_li,

doubt it is due to pix_clk_hz.
please refer to Sensor Pixel Clock session to review your sensor pixel clock rate.

Yes,pix_clk_hz has caught my attention.According to TC368543XBG_HDMI-CSI_Tv29p.excel, Setting Main_Parameters,for example:
Timing select:1600x1200@60fps
pclk=162,hs=64,hbp=192,h_act=1600,hfp=304,vs=3,vbp=46,v_act=1200,vfp=1
refclk=27MHz
PLL input clock=6.75MHz
CSI speed range=500M-1G
CSI lane = 4
fbd=96
prd=4
frs=0
csi speed/lane=648MHz

tc358743.c
my EDID is:
static u8 edid = {
0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00,
0x52, 0x62, 0x88, 0x88, 0x00, 0x88, 0x88, 0x88,
0x1C, 0x15, 0x01, 0x03, 0x80, 0x00, 0x00, 0x78,
0x0A, 0x0D, 0xC9, 0xA0, 0x57, 0x47, 0x98, 0x27,
0x12, 0x48, 0x4C, 0x00, 0x00, 0x00, 0x01, 0x01,
0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x48, 0x3F,
0x40, 0x30, 0x62, 0xB0, 0x32, 0x40, 0x40, 0xc0,
0x13, 0x00, 0xC0, 0x6C, 0x00, 0x00, 0x00, 0x1E,
0x01, 0x1D, 0x00, 0x72, 0x51, 0xD0, 0x1E, 0x20,
0x6E, 0x28, 0x55, 0x00, 0xC0, 0x6C, 0x00, 0x00,
0x00, 0x1E, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x54,
0x6F, 0x73, 0x68, 0x69, 0x62, 0x61, 0x2D, 0x48,
0x32, 0x43, 0x0A, 0x20, 0x00, 0x00, 0x00, 0xFD,
0x00, 0x14, 0x78, 0x01, 0xFF, 0x10, 0x00, 0x0A,
0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x01, 0xB0,
0x02, 0x03, 0x1A, 0xF1, 0x47, 0xC6, 0x04, 0x22,
0x02, 0x13, 0x1F, 0x20, 0x23, 0x09, 0x07, 0x01,
0x83, 0x01, 0x00, 0x00, 0x65, 0x03, 0x0C, 0x00,
0x10, 0x00, 0x01, 0x1D, 0x80, 0x18, 0x71, 0x38,
0x2D, 0x40, 0x58, 0x2C, 0x45, 0x00, 0xC0, 0x6C,
0x00, 0x00, 0x00, 0x1E, 0x8C, 0x0A, 0xD0, 0x8A,
0x20, 0xE0, 0x2D, 0x10, 0x10, 0x3E, 0x96, 0x00,
0xC0, 0x6C, 0x00, 0x00, 0x00, 0x18, 0x01, 0x1D,
0x00, 0xBC, 0x52, 0xD0, 0x1E, 0x20, 0xB8, 0x28,
0x55, 0x40, 0xC0, 0x6C, 0x00, 0x00, 0x00, 0x1E,
0x02, 0x3A, 0x80, 0xD0, 0x72, 0x38, 0x2D, 0x40,
0x10, 0x2C, 0x45, 0x80, 0xC0, 0x6C, 0x00, 0x00,
0x00, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x12,
};

static int tc358743_probe_of(struct tc358743_state *state)
{
struct device *dev = &state->i2c_client->dev;
struct v4l2_of_endpoint *endpoint;
struct device_node *ep;
// struct clk *refclk;
u32 bps_pr_lane;
int ret = -EINVAL;

ep = of_graph_get_next_endpoint(dev->of_node, NULL);
if (!ep) {
	dev_err(dev, "missing endpoint node\n");
	return -EINVAL;
}

endpoint = v4l2_of_alloc_parse_endpoint(ep);
if (IS_ERR(endpoint)) {
	dev_err(dev, "failed to parse endpoint\n");
	return PTR_ERR(endpoint);
}

if (endpoint->bus_type != V4L2_MBUS_CSI2 ||
    endpoint->bus.mipi_csi2.num_data_lanes == 0 ||
    endpoint->nr_of_link_frequencies == 0) {
	dev_err(dev, "missing CSI-2 properties in endpoint\n");
	goto free_endpoint;
}

state->bus = endpoint->bus.mipi_csi2;

// clk_prepare_enable(refclk);

//state->pdata.refclk_hz = clk_get_rate(refclk);
state->pdata.refclk_hz = 27000000;
state->pdata.ddc5v_delay = DDC5V_DELAY_100_MS;
state->pdata.enable_hdcp = false;
/* A FIFO level of 16 should be enough for 2-lane 720p60 at 594 MHz. */
state->pdata.fifo_level = 16;
/*
 * The PLL input clock is obtained by dividing refclk by pll_prd.
 * It must be between 6 MHz and 40 MHz, lower frequency is better.
 */
switch (state->pdata.refclk_hz) {
case 26000000:
case 27000000:
case 42000000:
	state->pdata.pll_prd = state->pdata.refclk_hz / 6750000;  //6M->6.75M  prd=4
	break;
default:
	dev_err(dev, "unsupported refclk rate: %u Hz\n", state->pdata.refclk_hz);
	goto disable_clk;
}

/*
 * The CSI bps per lane must be between 62.5 Mbps and 1 Gbps.
 * The default is 594 Mbps for 4-lane 1080p60 or 2-lane 720p60.
 */
//bps_pr_lane = 2 * endpoint->link_frequencies[0];
bps_pr_lane = 648000000;
if (bps_pr_lane < 62500000U || bps_pr_lane > 1000000000U) {
	dev_err(dev, "unsupported bps per lane: %u bps\n", bps_pr_lane);
	goto disable_clk;
}

/* The CSI speed per lane is refclk / pll_prd * pll_fbd */
state->pdata.pll_fbd = bps_pr_lane / state->pdata.refclk_hz * state->pdata.pll_prd;  //fbd=96

/*
 * FIXME: These timings are from REF_02 for 594 Mbps per lane (297 MHz
 * link frequency). In principle it should be possible to calculate
 * them based on link frequency and resolution.
 */
if (bps_pr_lane != 648000000U)   //594000000U->648000000U
	dev_warn(dev, "untested bps per lane: %u bps\n", bps_pr_lane);
state->pdata.lineinitcnt = 0x1388; //0xe80
state->pdata.lptxtimecnt = 0x004; //0x003
/* tclk-preparecnt: 3, tclk-zerocnt: 20 */
state->pdata.tclk_headercnt = 0x1903;  //0x1403
state->pdata.tclk_trailcnt = 0x01;    //0x00
/* ths-preparecnt: 3, ths-zerocnt: 1 */
state->pdata.ths_headercnt = 0x0204;
state->pdata.twakeup = 0x4650;   //0x4882
state->pdata.tclk_postcnt = 0x008;
state->pdata.ths_trailcnt = 0x03;
state->pdata.hstxvregcnt = 0X05;   //0

state->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);

if (IS_ERR(state->reset_gpio)) {
	dev_err(dev, "failed to get reset gpio\n");
	ret = PTR_ERR(state->reset_gpio);
	goto disable_clk;
}

if (state->reset_gpio)
	tc358743_gpio_reset(state);

ret = 0;
goto free_endpoint;

disable_clk:
// clk_disable_unprepare(refclk);
free_endpoint:
v4l2_of_free_endpoint(endpoint);
return ret;
}

static unsigned tc358743_num_csi_lanes_needed(struct v4l2_subdev *sd)
{
struct tc358743_state *state = to_state(sd);
struct v4l2_bt_timings *bt = &state->timings.bt;
struct tc358743_platform_data *pdata = &state->pdata;
//u32 bits_pr_pixel = (state->mbus_fmt_code == MEDIA_BUS_FMT_UYVY8_1X16) ? 16 : 24;
//u32 bps = bt->width * bt->height * fps(bt) * bits_pr_pixel;
u32 bps = bt->pixelclock * 1000000;
u32 bps_pr_lane = (pdata->refclk_hz / pdata->pll_prd) * pdata->pll_fbd;
return DIV_ROUND_UP(bps, bps_pr_lane);
}

hello Bit_li,

are you able to probe the signal?
furthermore, is it possible to enable test-pattern-generator to narrow down the issue?

hello JerryChang,thank you for your reply.
my project needs to adapt two timing, which are 1080p@60fps and 1600x1200@60fps. And the timing is generated by Hi3559A or Raspberry Pi HDMI port. I have already captured 1080p@60fps video successfully long before.
unfortunately, 1600x1200@60fps led me to get into trouble.
According to your suggestion, refer to Sensor Pixel Clock session, always still capture normally for a moment, can not capture for a moment. It’s so strange.
The source hdmi timing can enable my displayer, but I have no hardware-tools to get the output of Detailed Timing Parameters.sometimes I use One-to-Two Hdmi to suppress interference.

hello Bit_li,

I’m not fully understand your environment setups,
could you please have topology to demonstrate your hardware connections.
thanks


I drew a simple diagram。
For example,using Raspberry,in order to generate 1600x1200@fps, excute command:
xrandr --newmode “1600x1200@60.00” 162 1600 1664 1856 2160 1200 1201 1204 1250 -hsync +vsync
xrandr --addmode HDMI-1 “1600x1200@60.00”
Then,the Raspberry Displayer display 1600x1200@60.00 normally.But Jetson TX2i with TC358743XBG cann’t work.

Are you saying that you want to add mode by using xrandr? It is not supported on any jetson platform.

Only mode from edid or device tree is adopted.

Hello WayneWWW,thank you .

I don’t mean that. I need to capture 1600x1200 video from Raspberry or Hi3559 with HDMI. In order to generate the standard timing(1600x1200_60fps), I used xrandr command in Raspberry. By using tc358743xbg the jetson was able to get the video for further processing.
my kernel log explain sometimes normal, sometimes abnormal.


Hi,

What is the exact thing that this card trying to get from jetson?

Xrandr command is for the display driver to use.

Hi, WayneWWW,JerryChang. Thank you for your patient response. I have solved the problem.
First, checking the pix_clk_hz. please refer to Sensor Pixel Clock session to review your sensor pixel clock rate.
Second, checking the HDMI source, the driver will check and match the pix_clk_hz 、pll and other parameters one by one.
At last, if you feel the code no problem, it is important to choose a good hdmi cable. i replace the hdmi cable, the TMDS signal apperars now.

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