I am generating a color pattern via an FPGA and passing that through the MIPI port. I was wondering what the best way to visualize this pattern is. Should I be able to use the generic soc_camera_platform for this?
Hi ayodeji
Yes, for TK1 you should use the soc_camera to bring up your project.
Hello Shane,
Thank you for the response, I brought the soc_camera_plaform driver but I can’t seem to get any image. My test pattern is a Raw Bayer 12 format, so I added support for that in the vi and soc_camera drivers. If try to capture video, I get a syncpt error like this:
[ 291.153281] vi vi.0: CSI_A syncpt timeout, syncpt = 3, err = -11
[ 291.160041] TEGRA_CSI_CSI_CIL_A_STATUS 0x00000000
[ 291.164854] TEGRA_CSI_CSI_CILA_STATUS 0x00000000
[ 291.169618] TEGRA_CSI_CSI_CIL_B_STATUS 0x00000000
[ 291.174335] TEGRA_CSI_CSI_CIL_C_STATUS 0x00000000
[ 291.179068] TEGRA_CSI_CSI_CIL_D_STATUS 0x00000000
[ 291.183825] TEGRA_CSI_CSI_CIL_E_STATUS 0x00000000
[ 291.188542] TEGRA_CSI_CSI_PIXEL_PARSER_A_STATUS 0x00000000
[ 291.194045] TEGRA_CSI_CSI_PIXEL_PARSER_B_STATUS 0x00000000
[ 291.199529] TEGRA_VI_CSI_0_ERROR_STATUS 0x00000000
[ 291.204317] TEGRA_VI_CSI_1_ERROR_STATUS 0x00000000
I also tried accessing the CSI/VI registers from /dev/mem but that seems to crash the TK1.
Thanks!
The csi status REG all zero that could be there’s no validate data in the MIPI bus.
You have to scope the MIPI single to make sure of it.
Hey Shane!
It turns out I had some issues with the data format and the configuration settings in the board file. I am still getting syncpt errors though. It seems the errors I am getting in the register have to do with the frame size but I have verified this as best as I can and the data appears to be fine.
I am wondering if the fact that my mipi data from the fpga is streaming continuously is a problem. Would I need to have some way to start and stop the streaming to have the syncpt not fail?
Thanks
[ 291.153281] vi vi.0: CSI_A syncpt timeout, syncpt = 3, err = -11
[ 291.160041] TEGRA_CSI_CSI_CIL_A_STATUS 0x00000000
[ 291.164854] TEGRA_CSI_CSI_CILA_STATUS 0x00000000
[ 291.169618] TEGRA_CSI_CSI_CIL_B_STATUS 0x00000000
[ 291.174335] TEGRA_CSI_CSI_CIL_C_STATUS 0x00000000
[ 291.179068] TEGRA_CSI_CSI_CIL_D_STATUS 0x00000000
[ 291.183825] TEGRA_CSI_CSI_CIL_E_STATUS 0x00000000
[ 291.188542] TEGRA_CSI_CSI_PIXEL_PARSER_A_STATUS 0x00000000
[ 291.194045] TEGRA_CSI_CSI_PIXEL_PARSER_B_STATUS 0x00000094
[ 291.199529] TEGRA_VI_CSI_0_ERROR_STATUS 0x00000005
[ 291.204317] TEGRA_VI_CSI_1_ERROR_STATUS 0x00000000
The error status show the frame size is incorrect. Have a check the output size with sensor driver define.
I was able to resolve the issue with the frame size. I am now getting image data with no errors but I noticed something strange. I had everything working @ 1920x1080 but when I changed the frame size to 1440x1080, my data doesn’t come in as expected. The test data is designed such that each line has the same pixel value and it looks fine at 1920x1080 e.g. line 1 of a frame contains 1920 zeros and line 10 of a frame contains 1920 nines. At 1440x1080 line 1 should contain 1440 zeros but it instead has 1408 zeros and 32 ones. Each number representing a line is short by 32 and the last 24 lines are received as zeros.
Good Frame @ 1920x1080
[0 0 0 0 0 0 0 0 0 0]
[1 1 1 1 1 1 1 1 1 1]
[2 2 2 2 2 2 2 2 2 2]
Bad Frame @ 1440x1080
[0 0 0 0 0 0 0 1 1 1]
[1 1 1 1 2 2 2 2 2 2]
[2 0 0 0 0 0 0 0 0 0]
Hi ayodeji
Does the sensor output RAW12? Should two bytes a pixel?
hi Admin
How to get the spec
[quote=“ShaneCCC”]
The error status show the frame size is incorrect. Have a check the output size with sensor driver define.
Check the TK1 TRM from the download center.