TK1 - DSI/CSI x4 muxing details

Hello,

It seems that in Tegra K1, we can mux DSI-B pads (x4 lanes) either as CSI or DSI. But I could not find any information regarding where should I mux those pads. I mean, there should be a register (control/pinmux register) where I can tell, those pads (x4 lanes) should be muxed as CSI/DSI. Any information regarding this will be helpful.

Hi JaiAtEcon,

The pinmux configuration is represented in device tree.

For example:

diff --git a/arch/arm/boot/dts/tegra124-platforms/tegra124-jetson_tk1-pinmux-pm375-0000-c00-00.dtsi b/arch/arm/boot/dts/tegra124-platforms/tegra124-jetson_tk1-pinmux-pm375-0000-c00-00.dtsi
index 2c1ac29…db97cb0 100644
— a/arch/arm/boot/dts/tegra124-platforms/tegra124-jetson_tk1-pinmux-pm375-0000-c00-00.dtsi
+++ b/arch/arm/boot/dts/tegra124-platforms/tegra124-jetson_tk1-pinmux-pm375-0000-c00-00.dtsi
@@ -670,7 +670,7 @@

                    mipi_pad_ctrl_dsi_b {
                            nvidia,pins = "mipi_pad_ctrl_dsi_b";
  •                           nvidia,function = "dsi_b";
    
  •                           nvidia,function = "csi";
                      };

Hello glo,

Thanks for the answer. I can see those entries in the device tree.

Hi,

Can you help me on DSI Driver on Tegra K1? I have tried to integrate AUO MIPI LCD B101UAN01.7 into our customized system based on TEGRA K1 CPU. So far we have checked everything around connection to CPU and its schematics. It seems everything is correct. For the LCD, it has ORISE TECH OCT3108B-HV161 MIPI IC and it is different than usual MIPI LCDs. However, I have contacted with the technical team of AUO and they said this lcd passive type of MIPI LCD. There is no need of initiating code and special sequence. I have enabled TK1 DSI configuration on kernel and changed the values in many different ways according to the Technical Reference Manual of TK1. There is no success at all.

I hope that you can tell us what we do wrong.

Thanks,

TD

Under discussing in https://devtalk.nvidia.com/default/topic/949183/