TK1 GMI Pin mux

We are developing a system where the TK1 may have to interface to a Xilinx FPGA via the parallel interface. The documentation tells me that there is indeed a GMI interface for accessing NAND and NOR FLASH. When I look through the documentation the TRM tells me the Ball Name and Pin Mux Function for each of the balls I need.

Tables 130 and 131 in the TRM tell me that in the muxed and non muxed versions of the interface that DQ0 is on Ball name GMI_AD0 and teh Pin Mux Function is GMI_AD0. Thats great except no where else in any of the documentation I can find is GMI_AD0 mentioned. The same is true of the rest of the Data lines and all the control lines except DQ27-DQ31 which are on DAP1.

So does the GMI interface exist in the TK1? If it does then please can I be pointed to the correct documentation for the interface.

TK1 does not enable GMI for customer, most of GMI pins are used for other interface or not routed out. The TegraK1_Embedded_DG is the standard reference, function not mentioned in it will not be supported.

We’ve successfully used GMI (x8) on TK1. As I understand NVIDIA hasn’t officially validated this interface themselves and therefore they say they don’t support it. I suggest you try to find previous versions of the TK1 pinmux spreadsheet where GMI was still listed. That would show what pins GMI signals can be routed to.