TK1 Power Down Sequence


I am designing a custom card that uses the TK1 processor and I am interested in knowing more about the power down sequencing requirements of the part. The documentation for the parts shows the sequence necessary but I am curious what the outcome is if the rails/signals are not sequenced down as shown. The question I am trying to answer is whether the part can be damaged from improper power down sequencing or if the part will not be damaged but rather the IO may just be undefined during this time.

Also, please note that I am not employing a PMIC in this design so if there is support for spontaneous power removal within the Jetson design that involves the PMIC, that will not apply.

Thanks for the help!

Hi, as you can see in the doc: NVIDIA strongly recommends the following power-down sequence. Violating this sequence may cause permanent damage.

Thanks, Trumany. I did see that but generally speaking, when we have worked with similar parts in the past, the datasheet typically provides a general statement much like that when in reality the part cannot be damage via the power down sequence. Instead, however, the IO can be undefined and peripheral devices can potentially be written to, operated, etc.

Is is possible for someone at NVIDIA to confirm/deny this parts susceptibility WRT power down?

Thank you!

All we can provide about this are in released documents as you can find in download center. As far as I know, there are so many kinds of possibility of violating the sequence, and so will cause so many kinds of failure which are hard to guaranteed to be certain results. So the most important thing is to follow the sequence.