I am designing a custom card that uses the TK1 processor and I am interested in knowing more about the power down sequencing requirements of the part. The documentation for the parts shows the sequence necessary but I am curious what the outcome is if the rails/signals are not sequenced down as shown. The question I am trying to answer is whether the part can be damaged from improper power down sequencing or if the part will not be damaged but rather the IO may just be undefined during this time.
Also, please note that I am not employing a PMIC in this design so if there is support for spontaneous power removal within the Jetson design that involves the PMIC, that will not apply.
Thanks for the help!