turing architecture - page fault

Hello everyone,

I didn’t find any specific info on the page fault capability of the turing architecture.
Does it have the same capability than pascal ?


Yes, turing, volta, and pascal have that capability in an appropriate managed memory setting.

Nice !

And (I’m pushing a bit the scope of the initial question) does turing has the same “access counters” feature as the volta architecture ?

As far as I know, yes. This isn’t really a programmer-visible thing. It’s an underlying HW optimization for the page-migration engine. So its certainly possible that the underlying design has changed. Details about any differences, if any, compared to Volta, are unpublished AFAIK, and it’s not my role here to discuss unpublished, unobservable/undiscoverable characteristics of the CUDA GPU.

Thanks for the quick answers !