Two DSI monitors


we are currently output from our Jetson TX2i one DSI and one HDMI video output.

how should we configure the DT in order to provide anothe DSI output? I could not find any configuration on the web or in the TRM (which only provided the concepts).


2 DSI monitors are not verified on our side. So we don’t guarantee whether it would work or not.
You can try to search similar cases on forum first.


We’d like to activate the second DSI (DSI-1 or DSI-C) as we have some signal integrity issues on the first lanes (DSI-0 or DSI-A).

How should we do it?

There is nothing on the forum addressing this issue.



We do not need the Ganged mode we need the DSI-C in standalone mode, just two lanes out of DSI-C, just like DSI-A.

How should we do it?

Configure the same as DSI-A but with nvidia,dsi-instance to 2.

We have applied it and we get a DC value of 1.2[V] from DSI-C lanes.

I though maybe moving the DSI-C from nvdisplay@15200000 to nvdisplay@15210000
nvdisplay@15210000 {
status = “okay”;
nvidia,dc-flags = <TEGRA_DC_FLAG_ENABLED>;
nvidia,emc-clk-rate = <300000000>;
nvidia,fb-bpp = <32>; /* bits per pixel */
nvidia,fb-flags = <TEGRA_FB_FLIP_ON_PROBE>;
nvidia,fb-win = <3>;
win-mask = <0x18>;
//nvidia,dc-or-node = “/host1x/sor1”;
nvidia,dc-or-node = “/host1x/dsi”;
nvidia,cmu-enable = <1>;

any suggestions?


And did you change anything in dsi node?

nvdisplay has nothing to do with dsi-c…


I have set nvidia,dsi-instance = <2>;

regarding nvdisply I was under the impression from the TRM document that
nvdisplay@15200000 is HEAD0
nvdisplay@15210000 is HEAD1
nvdisplay@15220000 is HEAD2

and anyone of the “heads” can have either:
nvidia,dc-or-node = “/host1x/dsi”;
nvidia,dc-connector = <&dsi>;
nvidia,dc-or-node = “/host1x/sor1”;
nvidia,dc-connector = <&sor1>;
nvidia,dc-or-node = “/host1x/sor”;
nvidia,dc-connector = <&sor0>;

Did I get it wrong?

Can you share your full dmesg?

Your understanding to nvdisplay is correct. But putting dsi to which head is not what we concern now.

And the reason why I posted that topic to you is that there is a bug when you try to enable dsi A and C simultaneously.

dmesg DSI-C.txt (117.1 KB)

We are now trying to put DSI-C to HEAD0 instead of DSI-A. Assuming that we’ll see DSI-1 instead of DSI-0.

We can see on the linux Display app the DSI-C and we enable it but we are getting some timeout issues, per the attached file

Is there a forecast for solving the bug of simultaneous DSIs’ display?


Honestly speaking,

  1. Current information is not enough to debug. Also, I want to know why do you want to move dsi from head 0 to head 1? It seems pointless to do such change when you don’t know whether it could bring up or not. You should use the original setting first. At least head 0 is able to run dsi A.

  2. I don’t think this bug would be fixed in near future. If you want multiple display case, I would suggest you to use DP and HDMI.

We have a problematic signal layout for the lanes coming from HEAD0 as a result the 24bit signal (which comes at 445MHz instead of 297[MHz) for 16-bit) is corrupted for the signal to be parsed by the DSI Rx (implemented by the FPGA). The lanes from DSI-C are correct.

Does it make sense?


problematic signal layout for the lanes coming from HEAD0

Sorry that I cannot get it. Are you trying to say hardware design problem?

There is no “lanes coming out from HEAD0”.
HEAD0 is just a virtual concept. It does not mean any physical pin.

For example, SOR0 node which represent DP0 pins can be assigned to HEAD0. And it can be assigned to HEAD1 too. In each case (HEAD0/HEAD1), the hardware connection are same but just on different display controller. Different display controller means it is possible has different software configuration.

Thus, what you are trying to do is

You set DSI-C to either head0 or head 1 and the result are different. I would say this may be just because some other software configuration are different…

And if you can understand above, then “trying to put DSI-C to HEAD0 instead of DSI-A” is also not a very precise statement. What you really do is “putting dsi contoller as dc-connector to headX”. And what you need to do next is configure the dsi node to let it output signal from DSI-C.


I understand that the HEADs are virtual connection and eventually the physical output is via the DSI lanes. I meant that the DSI-A 4 lanes are incorrectly routed on the customer board, while the DSI-C 4 lanes are routed correctly - from the signal integrity prespective. That is the lanes of DSI-C are capable to convey the higher frequnce signals while those of DSI-A - cannot.

Now practically, I gave connected the dsi controller to HEAD0. How can I make HEAD0 route the signal to a panel that is attached to DSI-C only by setting nvidia,dsi-instance = <2>;? I have done it and I get no signal from the DSI-C lanes.

Could you suggest what next?

This is unknown. As I said in previous comment, we don’t verify DSI C.

I can offer you the dts document later and let you try if there is any property to configure.

Please refer to below file from rel-28 source.