I am using an FPGA to continuously transfer data in and out of the TX1 (28.2 release). If there is no GPU activity nor memcopies, the transfers are fine. However when I do have GPU activity or memory copies, then I am seeing latencies in reading from memory to PCIE that the FPGA can’t tolerate.
It seems that the SMMU or memory bus is prioritizing GPU access to memory over the PCIE. Is there a way that I can configure the TX1 to prioritize PCIE traffic?
In the TRM (pg 825) , I see the Tegra Snap Arbiter Tree which says that both PCIE and the GPU are on ring 2 of the tree. Can I change PCIE to an ISO client /i.e. ring 1 of the tree, so that I can meet latency requirements?