I’m a bit stumped: every other document on the X1 I’ve read indicates PCI-E 5GT/s support. However, page 25 of the OEM Design Guide(table 23), has the note “2.5GHz, half-rate architecture” for PCI-E data rate.
I have yet to find an explanation that sits well with me. Options I’ve considered:
- Does that mean the PCI-E lanes transmit two bits per clock? I haven't been able to find a PCI-E specification that allows two bits per clock.
- Is the controller limited to half-data rate on the number of transactions per second? That doesn't seem likely since TX and RX are at least conceptually independent and decoupled.
- Is the controller really limited to PCI-E 1.0 data rates? Everywhere else says it's not, and other forums posts claim PCI-E performance beyond 1.0 limits.
- Perhaps a misprint? It doesn't seem to be mentioned anywhere else.
Anyone have any insight as to what the OEM Design Guide means?