Actually, pci-tegra is not built as a module. There is “CONFIG_PCI_TEGRA=y” in .config.
Also, simply removing tegra_pcie_relax_enable does not make difference.
I found that “Device Control Register” is 0x2810 by default on my endpoint,
therefore, I had to explicitly call pcie_capability_clear_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_RELAX_EN); to clear it.
Now my question is about T_PCIE2_RP_DEVICE_CONTROL_STATUS register on TX1.
When I call pcie_capability_clear_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_RELAX_EN);
it only resets PCI_EXP_DEVCTL_RELAX_EN on the endpoint,
but T_PCIE2_RP_DEVICE_CONTROL_STATUS register at address 0x01001088 still remains 0x00002810.
Please, explain the meaning of bit  - T_PCIE2_RP_DEVICE_CONTROL_STATUS_ENABLE_RELAXED_ORDERING in T_PCIE2_RP_DEVICE_CONTROL_STATUS.
If this bit is set, would it allow TX1 to send transactions with Relaxed Ordering set?
I must ensure that no such relaxed transactions can be sent in either direction
because that would violate producer-consumer model and cause data corruption.
Please, tell me how to make sure that relaxed ordering is cleared in all necessary places.