TX1 serdes register Tuning

My team have a few questions on Rx serdes registers.

Would you be able to give us feedback on the following questions?

  1. What is difference between T_PCIE2_RP_ECTL_1_R1_RX_FELS_1C vs T_PCIE2_RP_ECTL_1_R2_RX_FELS_1C?

  2. What is RX_FELS_1C field used for?

  3. Any register or guidance for CDR bandwidth control?

  4. Does Tx1 PCIE serdes have a feature to scan receiver EYES? If it does, it will be useful to calculate width/height/jitter of receiver EYE.



Hello … ping

Hi saransaund,

The internal check is ongoing, will update when final result got.

For the first question, the first register is for GEN1 & the second for GEN2.