My team have a few questions on Rx serdes registers.
Would you be able to give us feedback on the following questions?
What is difference between T_PCIE2_RP_ECTL_1_R1_RX_FELS_1C vs T_PCIE2_RP_ECTL_1_R2_RX_FELS_1C?
What is RX_FELS_1C field used for?
Any register or guidance for CDR bandwidth control?
Does Tx1 PCIE serdes have a feature to scan receiver EYES? If it does, it will be useful to calculate width/height/jitter of receiver EYE.