TX1 To force those A57 cores running

To force those A57 cores running at the same time, you could refer below link to know how to do:
http://elinux.org/Jetson/TX1_Controlling_Performance
echo 1 > /sys/kernel/cluster/immediate
echo 1 > /sys/kernel/cluster/force
echo G > /sys/kernel/cluster/active
But I Can not see cluster in my demo,how to find the cluster and To force those A57 cores running?

Hi, TX1 with quad-core A57 doesn’t have multiple clusters, hence it doesn’t have sysfs cluster entries. It was TK1 with multiple switchable clusters (4+1 A15 with LP shadow core). The TX1 wiki article does not reference the cluster entries from your post.

Hi, TX1 has four A53 or four A57 from <Tegra_X1_TRM_DP07225001_v1.1p[1].pdf>,
42.3.3 A57/A53 4+4 Switched Cluster Implementation
Tegra X1 is a quad A57 and a quad A53 implementation. Both A57 and A53 are implementations of the ARMv8 architecture and support identical debug feature list. Either of the A57 or A53 can be active
at a given time based on a register bit setting in the Flow Controller. The interfaces from CoreSight do not change at all with this switched cluster implementation. The CCPLEX accepts the interfaces from CoreSight and guarantees that these are correctly routed to the currently active cluster. The cluster switch happens only in CC6 state where both the clusters are off. The same set of registers from CAR is used to control the resets and clock enables for both the clusters. Therefore, CoreSight RTL implementation assumes that there is only one cluster.
This also allows the debugger to identify a single set of ROM tables, either for the A53 or for A57.
where is wrong?

Hi dusty_nv
Refer to this article
https://devtalk.nvidia.com/default/topic/1006937/?comment=5140050
TX1 supports 4 A57 cores and 4 A53 cores, can all of these cores run at the same time? or when A57 cores running,then A53 cores stop or power off ? and vise versa?

Please refer to the latest documentation and datasheet, Jetson TX1 is quad-core A57 with A53 disabled due to libc runtime incompatibility between in-order and out-of-order execution, hence only A57 are fused and available. The thread you linked to above also confirmed the A53 are not available in this post: https://devtalk.nvidia.com/default/topic/1006937/jetson-tx1/about-cpu-cluster/post/5140056/#5140056