TX2 <--> ATMega328p (Arduino) via /dev/ttyTHS1

Hello All,

We’re having a strange issue communicating between the serial port of an Arduino Pro Mini (5V TTL level shifted down to 3.3V) and the /dev/ttyTHS1 port exposed as ‘UART2’ on the J120-IMU carrier board by Auvidea. We can get serial communications to work reliably at 115.2 kbaud, but only if both devices are configured for two stop bits (8N2). Has anyone else observed this issue or know why it’s occurring? The J120 carrier board does not expose the interface’s CTS and RTS lines, so hardware flow control is not an option unfortunately.


  • Ryan

I don’t know about the Auvidea board, but on the dev board it is known that you can use a single stop bit up to 115200, but it does require two stop bits at faster speeds.

Hi Linux,

I had seen that advice elsewhere as well. We were hoping someone might be able to call out the specific reason, section of the TRM, or UART datasheet specification which states the limit explicitly (I haven’t been able to find it yet despite searching). It would be really helpful to know the true root cause of the requirement and why or if implementing hardware flow control signals would fix it.

I can’t say for sure. One relevant reference to look at is this document: “Tegra X2 (Parker Series SoC) Errata”. Go here, and look for the one on Parker series:

Within the document search for “UART”. Depending on which UART you use, I suspect some other UARTs which interface to this UART might be more or less sensitive to the accuracy of the baud rate. But…it depends on the case. Two stop bits does give a better ability to adjust for jitter or clocks which are simply not as exact regardless of the cause.

I’d say this section from the doc you linked ~90% confirms the issue explicitly. Thanks for the tip! See below (kind of wonder what exactly is meant by option 2, operated at double the baud rate of the attached device and use a charge pump to half it?):

UART-1 UART does not meet +/- 4% Baud Tolerance


Tegra RX has limitation in one stop bit mode configuration that its baud rate needs to be always higher
than that of transmitter. Otherwise, the received data will have corruption/invalid framing errors.


  1. Use 2-stop bits configuration wherever possible
  2. If 1-stop bit configuration is to be used, program Tegra baud rate greater than Transmitter baudrate. Contact your NVIDIA representative for available divisors with different PLL sources to achieve required baud rate SW can choose the required divisor to match with the deviations supported by transmitter.
  3. Alternately, if there is at least 1 bit delay between characters, this limitation is not applicable.


Will not fix.