TX2 CSI Bayer format Device-tree form fpga

Robotics & Edge Computing Jetson Systems Jetson TX2
1

Hello,

I’m looking to modify tc358748 driver for a device which transmits RAW12 information over 4 CSI lanes into the TX2.
my dts file is this

tc358748@20 {
			compatible = "nvidia,tc358748";
			reg = <0x20>;
			devnode = "video0";
			physical_w = "3.674";
			physical_h = "2.738";
			avdd-reg = "vana";
			iovdd-reg = "vif";

			vertical-flip = "true";

			mode0 { // tc358748_MODE_768x576
				mclk_khz = "27000";
				num_lanes = "4";
				tegra_sinterface = "serial_a";
				discontinuous_clk = "no";
				dpcm_enable = "false";
				cil_settletime = "0";

				active_w = "768";
				active_h = "576";
				pixel_t = "bayer_bggr";
				readout_orientation = "90";
				line_length = "1843";
				inherent_gain = "1";
				mclk_multiplier = "6.67";
				pix_clk_hz = "27000000";

				min_gain_val = "1.0";
				max_gain_val = "16";
				min_hdr_ratio = "1";
				max_hdr_ratio = "64";
				min_framerate = "1.816577";
				max_framerate = "30";
				min_exp_time = "34";
				max_exp_time = "550385";
			};	


			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@0 {
					reg = <0>;
					tc358748_out0: endpoint {
						csi-port = <2>;
						bus-width = <4>;
						remote-endpoint = <&tc358748_csi_in0>;
					};
				};
			};
		};

is this correct?
thank all.

2

hello caysno,

it seems TC358748 is a bridge device for converting and transferring.
you could also refer to our reference driver and device tree for your implementation.

<kernel_src>/kernel/kernel-4.4/drivers/media/i2c/tc358840.c
<kernel_src>/hardware/nvidia/platform/t18x/quill/kernel-dts/quill-modules/tegra186-camera-imx274.dtsi

please also refer to Camera Software Development Solution for the applications using v4l2-ctl to access the camera device. thanks

3

thankyou.
but i donnot find How to calculate clk.
ex:

mclk_khz = "27000";
				num_lanes = "4";
				tegra_sinterface = "serial_a";
				discontinuous_clk = "no";
				dpcm_enable = "false";
				cil_settletime = "0";

				active_w = "640";
				active_h = "512";
				pixel_t = "bayer_bggr";
				readout_orientation = "90";
				line_length = "1084";
				inherent_gain = "1";
				mclk_multiplier = "6.67";
				pix_clk_hz = "27000000";

i donnot make sure pix_clk_hz 、mclk_khz and mclk_multiplier node value

4

hello caysno,

given some descriptions about properties settings,
mclk is the clock going “into” sensor. in general, sensor input clock frequency is between 6 to 27 MHz.
if your sensor specification provides PLL_multiplier, Pre/Post_divider settings, you could calculate the mclk_multiplier as below formula.

mclk_multiplier = PLL_multiplier/ Pre_divider/ Post_divider

please check the sensor specification to understand the output clock, then you should configure that clock rate as pix_clk_hz.
also, here’s formula of the pixel clock rate calculation for your reference.

pix_clk_hz =  mclk_khz * mclk_multiplier

BTW, since you had connect a bridge device to Tegra side, you could also enable test-pattern generator to verify the signaling.
thanks

5

thank you very March