TX2 DMA registers

Autonomous Machines Jetson & Embedded Systems Jetson TX2
1

Hello,

I am looking for the DMA (common and channel) register details in the TX2 TRM. There is a section on “13.8 General-Purpose Central DMA (GPC-DMA) Registers”. The first subsection under that is 13.8.1 GPCDMA_SCR_SCR_CH0_0 which starts at Offset: 0xf00. I am not able to find the details of DMA control registers (which I assume will have an offset of 0x0) and so on. Is it missing or am I looking in the wrong section?(Document ver: v1.0p dated June 21, 2017). Is there a later version of the document available?

In TX1 TRM, section 21.2.5 APB DMA Registers and 21.2.6 APB DMA Channel Registers covers the details.

NOTE: I am trying to port over a custom implementation of SPI driver from TX1 and TX2 and would like to remap the registers.

2

Will check if can public them.
What REG information you would like to know?

3

Thank you dear ShaneCCC,

We are looking for information related to DMA Common Status, CSR, requesters TX & RX, and channel registers - CSR, STA, CSRE (DMA Pause), TX & RX FIFO and word count, SRC & DST pointers. If you could share these, that would be great.

Thanks in advance.

4

Did you find this out? The current TX2 TRM doesn’t have the CSR register’s details, among the other GPCDMA registers.

I also was trying to implement a SPI driver with DMA, but wasn’t sure what value to set in the REQ_SEL field… among other things