TX2, DSI Video Output, Ganged Mode Left/Right, Device Tree Configuration Questions.

We have been able to configure DSI in non-ganged mode to output video out of DSI-A
only, and that is properly displayed.

We are now trying to configure the DSI output for Ganged Mode Left/Right split, 8 lanes total,
to drive two monitors.

The problem we are having is that we get a

tegradc 15200000.nvdisplay: dsi: video fifo overflow.

Message. the TRM says “LB_OVERFLOW: Indicates that a Line buffer overflow event happened”

On our video out we are getting occasional periodic drop outs of the horizontal sync pulses.

Question 1

Should there be one or two “dsi” sections in the device tree. I.E one that configures DSI-A and
DSI-C, or two, one for each. The nvidia,tegra186-dsi.txt document in the kernel/Documentation
tree under devicetree/bindings/video isn’t 100% clear.

Question 2

Is there timing configuration outside of the dsi/panel/display-timings/panel node that needs to match
the DSI clocking. We see that the parameters the display-timings panel such as hactive and
vactive are used to properly (we think) configure the ganged mode and the DSI output clock has
the value we expect.

Thanks in advance,

Cary

cobrien,

Before we look into dual DSI ganged mode,

May I ask have you ever done any reworks to your carrier board for dual-DSI? Do you follow the OEM produce design guide so that your carrier board connect signal DSI_C and DSI_D to your display controller?

There is a DSI-digital converter fpga, then a digital -> HDMI converter connected to each
DSI output. We are able to display video on either DSI-A or DSI-C individually in non-ganged
mode by setting nvidia,dsi-instance in the panel description to 0 (first output) or 2
(second output). The requirement is to drive 4 HDMI output total, so we need to use ganged
mode to drive DSI-A and DSI-C with the left and right halves of the image buffer respectively.

I checked with our hardware designer. his response is…

“The way we connect on our carrier board is using the dual Link mode
DSI-A (1 x 4) to one display, DSI –C (1 x 4) to a second display.”

Hope this answers your question.

Thanks again,

Cary

Thanks for you reply.

I am still checking the configuration internally.

cobrien,

Please help reply more detail.

  1. Are you looking to have 2 completely independent panels or 2 DSI links that drive same panel?
  2. If it is 2 separate panels, are they identical? E.g. same resolution, refresh rate, mode of operation (video or command mode)?
  3. Do they display the same frame on both panels simultaneously? That is just duplicating the frame on both panels (or)
  4. A single frame but frame is split such that left-section of the frame is displayed on 1 panel and right-section of the panel is displayed on other panel
  1. Are you looking to have 2 completely independent panels or 2 DSI links that drive same panel?

The goal is to drive 4 separate hdmi monitors from our custom TX2 carrier board, 2 via HDMI
(which work now), 2 via DSI. Each DSI output is connected to a DSI-Digital converter then a
Digital to HDMI converter. Note if we configure just one DSI output we can display the video
perfectly, i.e. the DSI to digital converters and the HDMI converters are operating properly.

  1. If it is 2 separate panels, are they identical? E.g. same resolution, refresh rate, mode of operation (video or command mode)?

Both outputs will be identical, video non burst mode with the same fixed frame rate and resolution,
ideally 60 hz 1080p.

  1. Do they display the same frame on both panels simultaneously? That is just duplicating the frame on both panels (or)
  2. A single frame but frame is split such that left-section of the frame is displayed on 1 panel and right-section of the panel is displayed on other panel

The second option, left on one display, right on the other.

Since there is only one display head, the plan is to configure a double-wide display output, and
show the left half on one screen and the right half on the other. Xorg will interpret this as
a single DSI-0 monitor, and the software will show the output for one screen in the left half
of the region, the output for the other in the right half of the display region. We will be
running custom display software (no window manger, cursor disabled).

I hope this information helps.

Thanks,

Cary

cobrien,

  1. Are you using rel-28.2 codebase?
  2. From above comment, single DSI case seems work. Is this with DSI non-Ganged mode with 4 lanes only from single head for single DSI output (or)
    When both DSI outputs are configured with Ganged mode from single head, but only one DSI output is working? (I guess it is the former one, but need double confirm from you)

1, We are using the R28.1 code base

  1. The case that is working is non-ganged mode (i.e. ganged-mode=0), 4 lanes out. This gives us
    one monitor driven from the DSI. We can configure this to output EITHER DSI-A ( nvidia,dsi-instance = 0)
    or DSI-C ( nvidia,dsi-instance=2). In both cases our DSi conversion to HTML circuitry
    operates properly.

Thanks,

Cary

Just for reference, I’m attaching the device tree configuration. This is decompiled
from the final .dtb so the definitions are missing, but it’s guaranteed to have all
the fields available to of_dsi.c and of_dc.c.

Large lookup tables and status = “Disabled” sections have been removed.

Note there is only one dsi section. Should there be two, one for DSI-A and one
for DSI-C? Looking at of_dsi.c this doesn’t seem necessary, but I could be
wrong.

Note we have tried many resolution combinations in addition to this one.

Cary

nvdisplay@15200000 {
			compatible = "nvidia,tegra186-dc";
			reg = <0x0 0x15200000 0x0 0x10000>;
			interrupts = <0x0 0x99 0x4>;
			win-mask = <0x7>;
			#stream-id-cells = <0x1>;
			nvidia,dc-ctrlnum = <0x0>;
			clocks = <0xbc 0xd 0x9c 0xd 0x9e 0xd 0x9b 0xd 0x9f 0xd 0xa0 0xd 0x9d 0xd 0x10d 0xd 0x207 0xd 0x210 0xd 0x206 0xd 0x10b 0xd 0x3a 0xd 0x261>;
			clock-names = "clk32k_in", "nvdisplay_disp", "nvdisplayhub", "nvdisplay_p0", "nvdisplay_p1", "nvdisplay_p2", "nvdisp_dsc", "pllp_display", "plld2", "plld3", "pll_d", "pll_d_out1", "disp1_emc", "emc_latency";
			resets = <0xd 0x5c 0xd 0x5d 0xd 0x5e 0xd 0x5f 0xd 0x60 0xd 0x61 0xd 0x62 0xd 0x59>;
			reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", "wgrp3", "wgrp4", "wgrp5", "head0";
			status = "ok";
			nvidia,dc-flags = <0x1>;
			nvidia,emc-rate = <0x11e1a300>;
			nvidia,fb-bpp = <0x20>;
			nvidia,fb-flags = <0x1>;
			nvidia,fb-win = <0x0>;
			nvidia,dc-or-node = "/host1x/dsi";
			nvidia,cmu-enable = <0x1>;
			avdd_lcd-supply = <0xbd>;
			dvdd_lcd-supply = <0xbe>;
			avdd_dsi_csi-supply = <0x2f>;
			outp-supply = <0xbf>;
			outn-supply = <0xc0>;
			vdd_lcd_bl-supply = <0x1a>;
			vdd_lcd_bl_en-supply = <0xc1>;
			avdd_hdmi-supply = <0xc2>;
			avdd_hdmi_pll-supply = <0xe>;
			vdd_hdmi_5v0-supply = <0xc3>;
			linux,phandle = <0x59>;
			phandle = <0x59>;
		};
// skipping HDMI heads...
		dsi {
			compatible = "nvidia,tegra186-dsi";
			reg = <0x0 0x15300000 0x0 0x40000 0x0 0x15400000 0x0 0x40000 0x0 0x15900000 0x0 0x40000 0x0 0x15940000 0x0 0x40000 0x0 0x15880000 0x0 0x10000>;
			clocks = <0xbc 0xd 0x73 0xd 0x75 0xd 0x76 0xd 0x77 0xd 0xe7 0xd 0xe8 0xd 0xe9 0xd 0xea>;
			clock-names = "clk32k_in", "dsi", "dsia_lp", "dsib", "dsib_lp", "dsic", "dsic_lp", "dsid", "dsid_lp";
			resets = <0xd 0x6 0xd 0x7 0xd 0x3f 0xd 0x40 0xd 0x91>;
			reset-names = "dsia", "dsib", "dsic", "dsid", "dsi_padctrl";
			nvidia,enable-hs-clk-in-lp-mode = <0x1>;
			pad-controllers = <0x10 0xf 0x10 0x10 0x10 0x11 0x10 0x12>;
			pad-names = "dsia", "dsib", "dsic", "dsid";
			status = "ok";
			nvidia,dsi-controller-vs = <0x1>;

			prod-settings {
				#prod-cells = <0x3>;

				dsi-padctrl-prod {
					prod = <0x24 0x3f0fc3f 0x0 0x28 0x333333 0x0 0x30 0xffffff 0x0 0x34 0xffffff 0x777777 0x54 0x3f0fc3f 0x0 0x58 0x333333 0x0 0x60 0xffffff 0x0 0x64 0xffffff 0x777777 0x84 0x3f0fc3f 0x0 0x88 0x333333 0x0 0x90 0xffffff 0x0 0x94 0xffffff 0x777777 0xb4 0x3f0fc3f 0x0 0xb8 0x333333 0x0 0xc0 0xffffff 0x0 0xc4 0xffffff 0x777777>;
				};
			};

				cmu {
					nvidia,cmu-csc = <0x100 0x0 0x0 0x0 0x100 0x0 0x0 0x0 0x100>;
					nvidia,cmu-lut2 = // removed
				};

				nvdisp-cmu {
					nvidia,panel-csc = <0xd581 0x2979 0xc5 0x0 0x831 0xcac1 0x20c 0x0 0x189 0x625 0xcc4a 0x0>;
					nvidia,cmu-lut = // removed
				};
			};

			panel-s-wqxga-10-1 {
				status = "ok";
				compatible = "s,wqxga-10-1";
				nvidia,dsi-instance = <0x0>;
				nvidia,dsi-n-data-lanes = <0x8>;
				nvidia,dsi-pixel-format = <0x3>;
				nvidia,dsi-refresh-rate = <0x3d>;
				nvidia,dsi-rated-refresh-rate = <0x3c>;
				nvidia,dsi-te-polarity-low = <0x1>;
				nvidia,dsi-video-data-type = <0x0>;
				nvidia,dsi-video-clock-mode = <0x0>;
				nvidia,dsi-ganged-type = <0x1>;
				nvidia,dsi-ganged-write-to-all-links = <0x1>;
				nvidia,dsi-controller-vs = <0x1>;
				nvidia,dsi-virtual-channel = <0x0>;
				nvidia,dsi-panel-reset = <0x1>;
				nvidia,dsi-power-saving-suspend = <0x0>;
				nvidia,dsi-lp00-pre-panel-wakeup = <0x1>;
				nvidia,dsi-suspend-aggr = <0x3>;
				nvidia,dsi-ulpm-not-support = <0x1>;
				nvidia,dsi-init-cmd = <0x0 0x29 0x3 0x0 0x0 0x10 0x0 0x2a 0x0 0x0 0x1 0x14 0x0 0x5 0x0 0x0 0x0 0x1 0x14 0x0 0x29 0x3 0x0 0x0 0x10 0x1 0x1 0x0 0x0 0x1 0x14 0x0 0x5 0x0 0x0 0x0 0x1 0x14 0x0 0x5 0x35 0x0 0x0 0x1 0x14 0x0 0x5 0x11 0x0 0x0 0x1 0x78 0x0 0x5 0x29 0x0 0x0 0x1 0x14 0x3 0x1 0x1 0x78>;
				nvidia,dsi-n-init-cmd = <0x10>;
				nvidia,dsi-suspend-cmd = <0x0 0x5 0x28 0x0 0x0 0x1 0x32 0x0 0x5 0x10 0x0 0x0 0x1 0xc8 0x0 0x5 0x34 0x0 0x0 0x1 0x14>;
				nvidia,dsi-n-suspend-cmd = <0x6>;
				nvidia,panel-rst-gpio = <0x12 0x7b 0x1>;
				nvidia,panel-bl-pwm-gpio = <0x1c 0x8 0x1>;
				nvidia,dsi-split-link-type = <0x0>;
				nvidia,dsi-video-burst-mode = <0x1>;
				linux,phandle = <0x12a>;
				phandle = <0x12a>;

				disp-default-out {
					nvidia,out-type = <0x2>;
					nvidia,out-width = <0xd8>;
					nvidia,out-height = <0x87>;
					nvidia,out-flags = <0x0>;
					nvidia,out-parent-clk = "pll_d";
					nvidia,out-xres = <0x780>;
					nvidia,out-yres = <0x438>;
					nvidia,out-rotation = <0x0>;
				};

				display-timings {

					3840x1080-32 {
						clock-frequency = <0x90013c0>;
						hactive = <0x1018>;
						vactive = <0x438>;
						hfront-porch = <0x58>;
						hback-porch = <0x94>;
						hsync-len = <0x2c>;
						vfront-porch = <0x4>;
						vback-porch = <0x24>;
						vsync-len = <0x5>;
						nvidia,h-ref-to-sync = <0x1>;
						nvidia,v-ref-to-sync = <0x1>;
					};
				};

	
				cmu {
					nvidia,cmu-csc = <0x105 0x3d5 0x24 0x3ea 0x121 0x3c1 0x2 0xa 0xf4>;
					nvidia,cmu-lut2 = // removed
				};
			};

cobrien,

I just got some comment from internal team. We don’t have any ganged mode -> 2 display panel case. The actual reason for that is we don’t support dual panels init/enable for ganged mode.

Ok, I guess that explains why we were having trouble getting this to work. Is this
a hardware/microcode limitation, or is a limitation of the linux dc/dsi drivers? We
can investigate modifications to the driver if the underlying hardware supports what
we are trying to do.

Thanks,

Cary

Cary,

This is a SW limitation (dc/dsi).

Ok good. We are comfortable modifying the kernel driver code in whatever way
is necessary. Can you provide any guidance on what will need to
be changed? Is there a driver guide? Are there other resources available?

Note we now have a DSI analyzer so we have much better information about what
is being output.

Thanks,

Cary

We have created a document that describes in detail the DSI output based on the results using the DSI signal analyzer. I will attempt to attach the document. I believe we are very, very close to getting it to work, but there are some timing or parameter mismatches that are causing an overflow somewhere in the processing pipeline.

Any insight would be much appreciated.

We can make configuration changes and run additional tests if that would help.

Thanks in Advance

Cary

Error in Left and Right ganged mode of Nvidia TX2-1.docx (1.63 MB)

Any more information about this? We are up against a deadline. Any support would help.

Thanks,

Cary

Cary,

We may not share anymore since this case is not in support scope. You could try to update the DSI_DSI_GANGED_MODE_START_0 and DSI_DSI_GANGED_MODE_SIZE_0 register.

The TX2 TRM has below section in MIPI-DSI section: Left-Right. “Programming guidelines/sequence and equations for Left-Right Ganged mode…”