Hi :
Why my TX2 DSIA CLK have no onutput,but D0~D3 work well?
Hi,
What does that mean? Did you enable anything in device tree for your DSI panel?
HI：
Thank you for your reply.
YES ，Everything I can do. As you can see bellow：
1.the panel-s-wuxga-8-0.dtsi
/ {
host1x {
dsi {
panel_s_wuxga_8_0: panel-s-wuxga-8-0 {
status = "okay";
compatible = "s,wuxga-8-0";
nvidia,dsi-instance = <DSI_INSTANCE_0>;
nvidia,dsi-n-data-lanes = <4>;
nvidia,dsi-pixel-format = <TEGRA_DSI_PIXEL_FORMAT_24BIT_P>;
nvidia,dsi-refresh-rate = <60>;
nvidia,dsi-video-data-type = <TEGRA_DSI_VIDEO_TYPE_VIDEO_MODE>;
nvidia,dsi-video-clock-mode = <TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS>;
nvidia,dsi-video-burst-mode = <TEGRA_DSI_VIDEO_NONE_BURST_MODE>;
/*
nvidia,dsi-ganged-type = <TEGRA_DSI_GANGED_SYMMETRIC_LEFT_RIGHT>;
nvidia,dsi-ganged-swap-links = <1>;
nvidia,dsi-ganged-write-to-all-links = <1>;
*/
nvidia,dsi-controller-vs = <DSI_VS_1>;
nvidia,dsi-virtual-channel = <TEGRA_DSI_VIRTUAL_CHANNEL_0>;
nvidia,dsi-panel-reset = <TEGRA_DSI_ENABLE>;
nvidia,dsi-ulpm-not-support = <TEGRA_DSI_ENABLE>;
nvidia,dsi-suspend-stop-stream-late = <TEGRA_DSI_ENABLE>;
nvidia,dsi-power-saving-suspend = <TEGRA_DSI_ENABLE>;
nvidia,default_color_space = <1>; /*default color profile:adobeRGB*/
nvidia,dsi-init-cmd =
/* Long Packet: <PACKETTYPE[u8] COMMANDID[u8] PAYLOADCOUNT[u16] ECC[u8] PAYLOAD[..] CHECKSUM[u16]> */
/* Short Packet: <PACKETTYPE[u8] COMMANDID[u8] DATA0[u8] DATA1[u8] ECC[u8]> */
/* For DSI packets each DT cell is interpreted as u8 not u32 */
<TEGRA_DSI_DELAY_MS 150>,
<TEGRA_DSI_PACKET_CMD DSI_GENERIC_LONG_WRITE 0x04 0x00 0x00 0xFF 0x98 0x81 0x03 0x00 0x00>,
<TEGRA_DSI_DELAY_MS 50>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x01 0x00 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x02 0x00 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x03 0x73 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x04 0x13 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x05 0x00 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x06 0x0A 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x07 0x05 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x08 0x00 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x09 0x28 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x0a 0x00 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x0b 0x00 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x0c 0x00 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x0d 0x28 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x0e 0x00 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x0f 0x28 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x10 0x28 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x11 0x00 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x12 0x00 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x13 0x00 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x14 0x00 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x15 0x00 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x16 0x00 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x17 0x00 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x18 0x00 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x19 0x00 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x1a 0x00 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x1b 0x00 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x1c 0x00 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x1d 0x00 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x1e 0x40 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x1f 0x80 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x20 0x06 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x21 0x01 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x22 0x00 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x23 0x00 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x24 0x00 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x25 0x00 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x26 0x00 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x27 0x00 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x28 0x33 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x29 0x33 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x2a 0x00 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x2b 0x00 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x2c 0x04 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x2d 0x04 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x2e 0x05 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x2f 0x05 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x30 0x00 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x31 0x00 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x32 0x31 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x33 0x00 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x34 0x00 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x35 0x0A 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x36 0x00 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x37 0x08 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x38 0x00 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x39 0x00 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x3a 0x00 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x3b 0x00 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x3c 0x00 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x3d 0x00 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x3e 0x00 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x3f 0x00 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x40 0x00 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x41 0x00 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x42 0x00 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x43 0x08 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x44 0x00 0x00>,
/*GIP_2*/ <TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x50 0x01 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x51 0x23 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x52 0x44 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x53 0x67 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x54 0x89 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x55 0xab 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x56 0x01 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x57 0x23 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x58 0x45 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x59 0x67 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x5a 0x89 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x5b 0xab 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x5c 0xcd 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x5d 0xef 0x00>,
/*GIP_3 */ <TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x5e 0x11 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x5f 0x02 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x60 0x08 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x61 0x0E 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x62 0x0F 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x63 0x0C 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x64 0x0D 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x65 0x17 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x66 0x01 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x67 0x01 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x68 0x02 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x69 0x02 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x6a 0x00 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x6b 0x00 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x6c 0x02 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x6d 0x02 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x6e 0x16 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x6f 0x16 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x70 0x06 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x71 0x06 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x72 0x07 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x73 0x07 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x74 0x02 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x75 0x02 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x76 0x08 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x77 0x0e 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x78 0x0f 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x79 0x0c 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x7a 0x0d 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x7b 0x17 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x7c 0x01 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x7d 0x01 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x7e 0x02 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x7f 0x02 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x80 0x00 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x81 0x00 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x82 0x02 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x83 0x02 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x84 0x16 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x85 0x16 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x86 0x06 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x87 0x06 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x88 0x07 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x89 0x07 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x8a 0x02 0x00>,
<TEGRA_DSI_DELAY_MS 20>,
<TEGRA_DSI_PACKET_CMD DSI_GENERIC_LONG_WRITE 0x04 0x00 0x00 0xFF 0x98 0x81 0x04 0x00 0x00>,
<TEGRA_DSI_DELAY_MS 20>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x6e 0x1a 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x6f 0x37 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x3a 0xa4 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x8d 0x1f 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x87 0xba 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xb2 0xd1 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x88 0x0b 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x38 0x01 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x39 0x00 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xb5 0x02 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x31 0x25 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x3b 0x98 0x00>,
<TEGRA_DSI_DELAY_MS 20>,
<TEGRA_DSI_PACKET_CMD DSI_GENERIC_LONG_WRITE 0x04 0x00 0x00 0xFF 0x98 0x81 0x01 0x00 0x00>,
<TEGRA_DSI_DELAY_MS 20>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x22 0x0a 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x31 0x00 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x53 0x53 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x55 0x3d 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x50 0x9e 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x51 0x99 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x60 0x06 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x62 0x20 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xa0 0x00 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xa1 0x17 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xa2 0x26 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xa3 0x13 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xa4 0x16 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xa5 0x29 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xa6 0x1e 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xa7 0x1f 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xa8 0x8b 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xa9 0x1d 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xaa 0x2a 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xab 0x7b 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xac 0x1a 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xad 0x19 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xae 0x4e 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xaf 0x24 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xb0 0x29 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xb1 0x4f 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xb2 0x5c 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xb3 0x23 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xc0 0x00 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xc1 0x17 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xc2 0x26 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xc3 0x13 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xc4 0x16 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xc5 0x29 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xc6 0x1e 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xc7 0x1f 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xc8 0x8b 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xc9 0x1d 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xca 0x2a 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xcb 0x7b 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xcc 0x1a 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xcd 0x19 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xce 0x4e 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xcf 0x24 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xd0 0x29 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xd1 0x4f 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xd2 0x5c 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xd3 0x23 0x00>,
<TEGRA_DSI_DELAY_MS 20>,
<TEGRA_DSI_PACKET_CMD DSI_GENERIC_LONG_WRITE 0x04 0x00 0x00 0xFF 0x98 0x81 0x00 0x00 0x00>,
<TEGRA_DSI_DELAY_MS 20>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_0_PARAM 0x11 0x00 0x00>,
<TEGRA_DSI_DELAY_MS 120>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_0_PARAM 0x29 0x00 0x00>,
<TEGRA_DSI_DELAY_MS 20>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_0_PARAM 0x35 0x00 0x00>,
<TEGRA_DSI_DELAY_MS 120>;
/* This panel has a very sensitive power on/off sequence.
* Send a few more frames for safety. No max limit from vendor. */
nvidia,dsi-n-init-cmd = <205>;
nvidia,dsi-suspend-cmd =
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_0_PARAM DSI_DCS_SET_DISPLAY_OFF 0x0 0x0>,
<TEGRA_DSI_SEND_FRAME 3>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_0_PARAM DSI_DCS_ENTER_SLEEP_MODE 0x0 0x0>,
<TEGRA_DSI_SEND_FRAME 10>;
nvidia,dsi-n-suspend-cmd = <4>;
/*
nvidia,dsi-pkt-seq =
<CMD_VS LEN_SHORT PKT_LP LINE_STOP>,
<CMD_HS LEN_SHORT PKT_LP LINE_STOP>,
<CMD_HS LEN_SHORT PKT_LP LINE_STOP>,
<CMD_HS LEN_SHORT CMD_RGB_24BPP LEN_HACTIVE3 CMD_BLNK LEN_HFP LINE_STOP>,
<CMD_HS LEN_SHORT PKT_LP LINE_STOP>,
<CMD_HS LEN_SHORT CMD_RGB_24BPP LEN_HACTIVE3 CMD_BLNK LEN_HFP LINE_STOP>;
*/
disp-default-out {
nvidia,out-type = <TEGRA_DC_OUT_DSI>;
nvidia,out-width = <154>;
nvidia,out-height = <85>;
nvidia,out-flags = <TEGRA_DC_OUT_CONTINUOUS_MODE>;
nvidia,out-parent-clk = "pll_d_out0";
nvidia,out-xres = <1280>;
nvidia,out-yres = <800>;
};
display-timings {
1200x1920-32-60Hz {
clock-frequency = <5000000>;
hactive = <1280>;
vactive = <800>;
hfront-porch = <8>;
hback-porch = <16>;
hsync-len = <18>;
hsync-active = <2>;
vfront-porch = <14>;
vback-porch = <38>;
vsync-len = <4>;
vsync-active = <2>;
nvidia,h-ref-to-sync = <0>;
nvidia,v-ref-to-sync = <0>;
};
};
smartdimmer {
status = "okay";
nvidia,turn-off-brightness = <50>;
nvidia,turn-on-brightness = <75>;
nvidia,use-auto-pwm = <0>;
nvidia,hw-update-delay = <0>;
nvidia,bin-width = <0xffffffff>;
nvidia,aggressiveness = <5>;
nvidia,use-vid-luma = <0>;
nvidia,phase-in-settings = <0>;
nvidia,phase-in-adjustments = <0>;
nvidia,k-limit-enable = <1>;
nvidia,k-limit = <200>;
nvidia,sd-window-enable = <0>;
nvidia,soft-clipping-enable= <1>;
nvidia,soft-clipping-threshold = <128>;
nvidia,smooth-k-enable = <1>;
nvidia,smooth-k-incr = <4>;
nvidia,coeff = <5 9 2>;
nvidia,fc = <0 0>;
nvidia,blp = <1024 255>;
nvidia,bltf = <57 65 73 82
92 103 114 125
138 150 164 178
193 208 224 241>;
nvidia,lut = <255 255 255
199 199 199
153 153 153
116 116 116
85 85 85
59 59 59
36 36 36
17 17 17
0 0 0>;
nvidia,use-vpulse2 = <1>;
nvidia,bl-device-name = "pwm-backlight";
};
cmu {
nvidia,cmu-csc = < 0x100 0x0 0x0
0x0 0x100 0x0
0x0 0x0 0x100 >;
nvidia,cmu-lut2 = < 0 1 2 2 3 4 5 6
6 7 8 9 10 10 11 12
13 13 14 15 15 16 16 17
18 18 19 19 20 20 21 21
22 22 23 23 23 24 24 25
25 25 26 26 27 27 27 28
28 29 29 29 30 30 30 31
31 31 32 32 32 33 33 33
34 34 34 34 35 35 35 36
36 36 37 37 37 37 38 38
38 38 39 39 39 40 40 40
40 41 41 41 41 42 42 42
42 43 43 43 43 43 44 44
44 44 45 45 45 45 46 46
46 46 46 47 47 47 47 48
48 48 48 48 49 49 49 49
49 50 50 50 50 50 51 51
51 51 51 52 52 52 52 52
53 53 53 53 53 54 54 54
54 54 55 55 55 55 55 55
56 56 56 56 56 57 57 57
57 57 57 58 58 58 58 58
58 59 59 59 59 59 59 60
60 60 60 60 60 61 61 61
61 61 61 62 62 62 62 62
62 63 63 63 63 63 63 64
64 64 64 64 64 64 65 65
65 65 65 65 66 66 66 66
66 66 66 67 67 67 67 67
67 67 68 68 68 68 68 68
68 69 69 69 69 69 69 69
70 70 70 70 70 70 70 71
71 71 71 71 71 71 72 72
72 72 72 72 72 72 73 73
73 73 73 73 73 74 74 74
74 74 74 74 74 75 75 75
75 75 75 75 75 76 76 76
76 76 76 76 77 77 77 77
77 77 77 77 78 78 78 78
78 78 78 78 78 79 79 79
79 79 79 79 79 80 80 80
80 80 80 80 80 81 81 81
81 81 81 81 81 81 82 82
82 82 82 82 82 82 83 83
83 83 83 83 83 83 83 84
84 84 84 84 84 84 84 84
85 85 85 85 85 85 85 85
85 86 86 86 86 86 86 86
86 86 87 87 87 87 87 87
87 87 87 88 88 88 88 88
88 88 88 88 88 89 89 89
89 89 89 89 89 89 90 90
90 90 90 90 90 90 90 90
91 91 91 91 91 91 91 91
91 91 92 92 92 92 92 92
92 92 92 92 93 93 93 93
93 93 93 93 93 93 94 94
94 94 94 94 94 94 94 94
95 95 95 95 95 95 95 95
95 95 96 96 96 96 96 96
96 96 96 96 96 97 97 97
97 97 97 97 97 97 97 98
98 98 98 98 98 98 98 98
98 98 99 99 99 99 99 99
99 100 101 101 102 103 103 104
105 105 106 107 107 108 109 109
110 111 111 112 113 113 114 115
115 116 116 117 118 118 119 119
120 120 121 122 122 123 123 124
124 125 126 126 127 127 128 128
129 129 130 130 131 131 132 132
133 133 134 134 135 135 136 136
137 137 138 138 139 139 140 140
141 141 142 142 143 143 144 144
145 145 145 146 146 147 147 148
148 149 149 150 150 150 151 151
152 152 153 153 153 154 154 155
155 156 156 156 157 157 158 158
158 159 159 160 160 160 161 161
162 162 162 163 163 164 164 164
165 165 166 166 166 167 167 167
168 168 169 169 169 170 170 170
171 171 172 172 172 173 173 173
174 174 174 175 175 176 176 176
177 177 177 178 178 178 179 179
179 180 180 180 181 181 182 182
182 183 183 183 184 184 184 185
185 185 186 186 186 187 187 187
188 188 188 189 189 189 189 190
190 190 191 191 191 192 192 192
193 193 193 194 194 194 195 195
195 196 196 196 196 197 197 197
198 198 198 199 199 199 200 200
200 200 201 201 201 202 202 202
202 203 203 203 204 204 204 205
205 205 205 206 206 206 207 207
207 207 208 208 208 209 209 209
209 210 210 210 211 211 211 211
212 212 212 213 213 213 213 214
214 214 214 215 215 215 216 216
216 216 217 217 217 217 218 218
218 219 219 219 219 220 220 220
220 221 221 221 221 222 222 222
223 223 223 223 224 224 224 224
225 225 225 225 226 226 226 226
227 227 227 227 228 228 228 228
229 229 229 229 230 230 230 230
231 231 231 231 232 232 232 232
233 233 233 233 234 234 234 234
235 235 235 235 236 236 236 236
237 237 237 237 238 238 238 238
239 239 239 239 240 240 240 240
240 241 241 241 241 242 242 242
242 243 243 243 243 244 244 244
244 244 245 245 245 245 246 246
246 246 247 247 247 247 247 248
248 248 248 249 249 249 249 249
250 250 250 250 251 251 251 251
251 252 252 252 252 253 253 253
253 253 254 254 254 254 255 255 >;
};
};
};
};
backlight {
panel_s_wuxga_8_0_bl: panel-s-wuxga-8-0-bl {
status = "okay";
compatible = "s,wuxga-8-0-bl";
pwms = <&tegra_pwm 0 40161>;
max-brightness = <255>;
default-brightness = <191>;
default-charge-brightness = <112>;
bl-measured = < 0 1 2 3 4 5 5 6
7 8 9 10 11 11 12 13
14 15 15 16 17 18 19 20
21 22 22 23 24 25 26 27
28 29 30 31 31 32 33 34
35 36 37 37 38 39 40 41
41 42 43 44 45 46 47 48
48 49 50 51 52 53 54 54
55 56 57 58 58 59 60 61
62 63 64 65 66 67 68 69
70 71 72 73 74 75 75 76
77 78 79 80 81 82 83 84
85 86 87 88 89 90 91 92
93 94 94 95 96 97 98 99
100 101 102 104 105 106 107 108
109 110 111 112 113 114 115 116
117 118 119 120 121 122 123 125
126 127 128 129 130 131 132 133
134 135 136 137 138 139 140 141
142 143 144 146 147 148 149 150
151 152 153 154 155 156 157 158
159 160 161 162 163 164 165 167
168 169 170 171 172 173 174 175
176 178 179 180 181 182 183 184
185 186 187 188 189 190 191 192
193 194 195 196 197 199 200 201
202 203 204 205 206 207 208 210
211 212 213 214 215 216 217 219
220 221 222 223 225 226 227 228
229 230 231 233 234 235 236 237
238 239 240 241 242 244 245 246
247 248 249 250 251 253 254 255 >;
};
};
2.the tegra186-quill-p3310-c03-00-base.dts
/ {
nvidia,dtsfilename = __FILE__;
nvidia,dtbbuildtime = __DATE__, __TIME__;
nvidia,fastboot-usb-vid = <0x0955>;
nvidia,fastboot-usb-pid = <0xee16>;
pinmux@2430000 {
common {
gpio_edp2_pp5 {
status = "okay";
};
gpio_edp3_pp6 {
status = "okay";
};
};
};
gpio@2200000 {
/* gpio-name for 40-pin header, gpio-name given as COL(10) x ROW(20) */
gpio-line-names = "", "", "", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "", "GPIO8_ALS_PROX_INT", "GPIO11_AP_WAKE_BT",
"", "", "I2S0_CLK", "I2S0_SDOUT", "I2S0_SDIN", "I2S0_LRCLK", "AUDIO_MCLK", "GPIO20_AUD_INT", "GPIO1_AUD_RST", "",
"", "", "", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "SPI1_CLK", "SPI1_MISO", "SPI1_MOSI",
"SPI1_CS0", "", "", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "", "", "",
"", "", "", "", "", "", "UART0_RTS", "UART0_CTS", "", "",
"", "", "", "", "", "", "", "", "", "",
"", "GPIO16_MDM_WAKE_AP", "", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "", "", "";
sdmmc-wake-support-input {
status = "okay";
};
sdmmc-wake-support-output {
status = "okay";
};
};
gpio@c2f0000 {
/* gpio-name for 40-pin header, gpio-name given as COL(10) x ROW(20) */
gpio-line-names = "", "", "", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "", "", "",
"AO_DMIC_IN_DAT", "AO_DMIC_IN_CLK", "GPIO9_MOTION_INT", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "", "", "";
};
fixed-regulators {
regulator@1 {
gpio = <&tegra_main_gpio TEGRA_MAIN_GPIO(P, 6) 0>;
};
};
sdhci@3400000 {
cd-gpios = <&tegra_main_gpio TEGRA_MAIN_GPIO(P, 5) 0>;
nvidia,cd-wakeup-capable;
};
hdr40_i2c0: i2c@3160000 {
ina3221x@40 {
channel@0 {
ti,shunt-resistor-mohm = <10>;
};
channel@1 {
ti,shunt-resistor-mohm = <10>;
};
};
ina3221x@41 {
channel@0 {
ti,shunt-resistor-mohm = <20>;
};
channel@1 {
ti,shunt-resistor-mohm = <10>;
};
channel@2 {
ti,rail-name = "VDD_SYS_DDR";
ti,shunt-resistor-mohm = <10>;
};
};
};
hdr40_i2c1: i2c@c240000 {
bmi160@69 {
compatible = "bmi,bmi160";
reg = <0x69>;
interrupt-parent = <&tegra_aon_gpio>;
interrupts = <TEGRA_AON_GPIO(AA, 2) 0x01>;
accelerometer_matrix = [01 00 00 00 01 00 00 00 01];
gyroscope_matrix = [01 00 00 00 01 00 00 00 01];
accelerometer_delay_us_min = <1250>;
gyroscope_delay_us_min = <1250>;
vdd-supply = <&spmic_sd3>;
vdd_IO-supply = <&spmic_sd3>;
status = "disabled";
};
};
mttcan@c310000 {
status = "okay";
gpio_can_stb = <&tegra_aon_gpio TEGRA_AON_GPIO(AA, 0) GPIO_ACTIVE_HIGH>;
gpio_can_en = <&tegra_aon_gpio TEGRA_AON_GPIO(AA, 1) GPIO_ACTIVE_HIGH>;
};
mttcan@c320000 {
status = "okay";
gpio_can_stb = <&tegra_aon_gpio TEGRA_AON_GPIO(AA, 6) GPIO_ACTIVE_HIGH>;
gpio_can_en = <&tegra_aon_gpio TEGRA_AON_GPIO(AA, 7) GPIO_ACTIVE_HIGH>;
};
ahci-sata@3507000 {
gpios = <&spmic 7 0>;
};
pcie-controller@10003000 {
pci@1,0 {
nvidia,num-lanes = <4>;
nvidia,disable-clock-request;
};
pci@2,0 {
nvidia,num-lanes = <0>;
};
pci@3,0 {
nvidia,num-lanes = <1>;
};
};
xhci@3530000 {
phys = <&{/xusb_padctl@3520000/pads/usb2/lanes/usb2-0}>,
<&{/xusb_padctl@3520000/pads/usb2/lanes/usb2-1}>,
<&{/xusb_padctl@3520000/pads/usb2/lanes/usb2-2}>,
<&{/xusb_padctl@3520000/pads/usb3/lanes/usb3-0}>;
phy-names = "usb2-0", "usb2-1", "usb2-2", "usb3-0";
nvidia,boost_cpu_freq = <1200>;
};
xusb_padctl@3520000 {
ports {
usb3-1 {
status = "disabled";
};
usb3-0 {
nvidia,usb2-companion = <1>;
status = "okay";
};
};
};
bluedroid_pm {
bluedroid_pm,reset-gpio = <&tegra_main_gpio TEGRA_MAIN_GPIO(H, 5) 0>;
};
bpmp_i2c {
spmic@3c {
pinmux@0 {
pin_gpio2 {
status = "disabled";
};
pin_gpio3 {
status = "disabled";
};
pin_gpio7 {
drive-push-pull = <1>;
};
};
regulators {
ldo0 {
maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
};
ldo6 {
maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
regulator-boot-on;
regulator-always-on;
};
ldo7 {
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
};
ldo8 {
regulator-name = "dvdd-pex";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
};
};
};
};
host1x {
nvdisplay@15200000 {
status = "okay";
nvidia,dc-or-node = "/host1x/dsi";
};
dsi {
status = "okay";
nvidia,active-panel = <&panel_s_wuxga_8_0>;
panel-s-wuxga-8-0 {
status = "okay";
};
};
};
sound {
hdr40_snd_link_i2s: nvidia,dai-link-1 { };
};
};
Please help me.
Any dmesg to share?
Hello :
This problem has been solved。I have another question ,How to enable the U-BOOT use the DSI panel ?
Could you share how it’s resovled?
And please open another topic.
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