TX2 failed to receive image data if MIPI lane bitrate larger than 800Mbps

Autonomous Machines Jetson & Embedded Systems Jetson TX2
#1

The platform is TX2 / Linux BSP 32.2.3.
Hardware configuration is as follows:

sensor–> TI DS90UB953 (serializer)--------TI DS90UB960 (deserializer)–> TX2 MIPI CSI2(4 lane)

The problem is:
TX2 failed to receive image data from MIPI CSI2 if the UB960(deserializer) 's MIPI lane bitrate is set to 1.2Gbps or higher( such as 1.6Gbps), while everything works fine with 800Mbps MIPI lane.

We encountered the similar problem with NextChip’s N4 chip:
4 AHD camera(1280x720@30fps) -->N4 --> TX2 MIPI CSI2(4 lane)
System works fine with 800Mbps MIPI lane, while image receive error occurs with 1.2G/1.6Gbps MIPI lane (for 1080P@30fps input).
Note, the same hardware and register setting works fine on NXP imx6/imx8 platform.

How to fix the aforementioned problem?
Is there anything special that should be done with TX2 MIPI CSI2 interface when dealing with 1.6Gbps/lane MIPI input?

#4

Assume you are testing on dev kit. There is max trace delay limit in OEM Design Guide as you can see in the MIPI DSI & CSI Interface Signal Routing Requirements table (paste below). The delay of CSI on devkit carrier board is about 600ps, so the real data rate depends on the delay of carrier board + camera module board. This delay limits the final data rate.

1000 ps @ 1 Gbps
800 ps @ 1.5 Gbps
350 ps @ 2.5 Gbps

#5

Actually we are testing on a customized board.
The deserializer is TI DS90UB960-Q1 quad FPD-Link III deserializer hub.

We checked the PCB trace delay carefully, according to the OEM Design Guide.
We confirm that the MIPI CSI-2 trace and layout satisfy the OEM DG requirements:

  1. The max trace length is less than 2800mil, which is approximately less than 540ps.
  2. the Intra-pair length mismatch is less than 5mil, so the intra-pair skew is less than 1ps;
  3. the inter-pair length mismatch is less than 10mil, so the inter-pair skew is less than 5ps.

So it should not be the delay that limits the data rate on our board.

By the way, when setting 960 to work at 1.6Gbps,
TX2 kernel dmesg outputs when we capture image:

[ 952.647611] tegra-vi4 15700000.vi: Status: 2 channel:00 frame:0005
[ 952.653936] tegra-vi4 15700000.vi: timestamp sof 964145072288 eof 964178328000 data 0x000000a4
[ 952.662997] tegra-vi4 15700000.vi: capture_id 161 stream 4 vchan 0
[ 952.815984] tegra-vi4 15700000.vi: PXL_SOF syncpt timeout! err = -11
[ 952.815998] tegra-vi4 15700000.vi: ATOMP_FE syncpt timeout! err = -11
[ 952.829808] nvcsi 150c0000.nvcsi: csi4_stream_check_status (4) ERROR_STATUS2VI_VC0 = 0x00000006
[ 952.839404] nvcsi 150c0000.nvcsi: csi4_stream_check_status (4) ERROR_STATUS2VI_VC1 = 0x00000004
[ 952.848227] nvcsi 150c0000.nvcsi: csi4_stream_check_status (4) INTR_STATUS 0x00010066
[ 952.856213] nvcsi 150c0000.nvcsi: csi4_stream_check_status (4) ERR_INTR_STATUS 0x00010066

According to TRM, seems there are some CRC / ECC errors.

Updated experimental results:
When setting MIPI CSI-2 lane bitrate to 1.2Gbps,
system works fine with 2-lane (1.2Gbps/lane) settings,
but failed to capture image with 4-lane (1.2Gbps/lane) settings.
However, with 1.6Gbps/lane setting,
both 2-lane and 4-lane setting failed.

Any idea?
Is this related to MIPI timing configuration?

#7

For the crc error you can try to modify the csi4_fops.c to configure the REG NVCSI_STREAM_0_ERROR_STATUS2VI_MASK_0 to try.

diff --git a/drivers/media/platform/tegra/camera/csi/csi4_fops.c b/drivers/media/platform/tegra/camera/csi/csi4_fops.c
index 0377d7b..b3d01d3 100644
--- a/drivers/media/platform/tegra/camera/csi/csi4_fops.c
+++ b/drivers/media/platform/tegra/camera/csi/csi4_fops.c
@@ -76,8 +76,18 @@ static void csi4_stream_init(struct tegra_csi_channel *chan, int port_num)
        csi4_stream_write(chan, port_num, INTR_STATUS, 0x3ffff);
        csi4_stream_write(chan, port_num, ERR_INTR_STATUS, 0x7ffff);
        csi4_stream_write(chan, port_num, ERROR_STATUS2VI_MASK, 0x0);
-       csi4_stream_write(chan, port_num, INTR_MASK, 0x0);
-       csi4_stream_write(chan, port_num, ERR_INTR_MASK, 0x0);
+
+       csi4_stream_write(chan, port_num, INTR_MASK, PH_ECC_MULTI_BIT_ERR |
+                       PD_CRC_ERR_VC0 | PH_ECC_SINGLE_BIT_ERR_VC0);
+       csi4_stream_write(chan, port_num, ERR_INTR_MASK, PH_ECC_MULTI_BIT_ERR |
+                       PD_CRC_ERR_VC0 | PH_ECC_SINGLE_BIT_ERR_VC0);
+       csi4_stream_write(chan, port_num, ERROR_STATUS2VI_MASK,
+                       CFG_ERR_STATUS2VI_MASK_VC0 |
+                       CFG_ERR_STATUS2VI_MASK_VC1 |
+                       CFG_ERR_STATUS2VI_MASK_VC2 |
+                       CFG_ERR_STATUS2VI_MASK_VC3);
 }
#9