TX2 I2C Slave Controller in Packet Mode


The TRM for the TX2 defines only the IO Packet header for the Master Controller not the Slave Controller. Does anyone know where this is defined? The slave controller seems to have support for packet mode but little info is given in the TRM about this, does it use the same IO header word?

Only master mode is supported on TX2 I2C ports.

The TRM definitely indicates that there is a slave controller as well, is it incorrect? There are a ton of I2C slave controller registers. Do they just not work? This explains why I was having trouble getting the slave controller working at all, if true.

Or do you just mean only master mode supports the packet FIFO, in which case the I2C_I2C_SLV_TX_PACKET_FIFO_0 register is not relevant on the tx2

TRM is for chip level features, some features of it are not implemented/validated on Jetson platform. For Jetson TX2, only master mode is supported.

If I understand you correctly, despite what the TRM says about the Tegra186 chip’s I2C modules, the actual manufactured hardware is something totally different? That’s… incredibly frustrating. Is there some documentation of these what other features I should avoid because they weren’t implemented?

The fact that the manual is so incredibly wrong in this way is very unsettling, but thank you for saving me a lot of headaches trying to make something work that isn’t possible.

That’s not the hardware thing only. The function needs to be validated on specific platform if necessary. You can check the OEM Product Design Guide for the I2C part features and design examples. No slave mode design supported is listed in it.

So there might be slave controllers on the I2C modules, but they aren’t validated/tested if they are there. I see that guide doesn’t mention slave mode support. However, both the TRM and the TX2 Data Sheet explicitly say that slave mode is supported.

I would strongly recommend that NVIDIA change this language, to indicate that this feature is in fact not supported. Developers and researchers like me would be more encouraged to use the platform with more clear documentation.


The I2C controller supports the following operating modes: Master – Standard-mode (up to 100Kbit/s), Fast-mode (up to 400 Kbit/s), Fast-mode plus (Fm+, up to 1Mbit/s); Slave – Standard-mode (up to 100Kbit/s), Fast-mode (up to 400 Kbit/s), Fast-mode plus (Fm+, up to 1Mbit/s).


The I2C controller can work both as a master and as a slave. The master can address the internal slave (for basic testing) or an external 7-bit or 10-bit addressed slave device.

Note that both these other documents also are semi-unified in stating what isn’t supported (high-speed mode, 10-bit addressing, multi-master mode). Seems like not supporting slave mode, should be mentioned there as well.