Tx2 jtag

I’m interested in getting the TX2 Dev Kit JTAG working with the TX2 developer kit. Is there anyone that could provide some guidance? Searches have yielded very little information. We have a flyswatter2 debugger which uses open-ocd. From what I can tell it should be possible but no configurations exist for this board/target combo. This would be a very valuable resource for me, and I’m sure it would help others in TX2 development. Just wondering if anyone has had success with anything like this and if anyone is willing to provide guidance/help that they’ve gotten in this area. Thank you.

Have a check the lauterbach.

https://elinux.org/Jetson/JTAG
https://developer.nvidia.com/embedded/dlc/r32-3-1_Release_v1.0/t186ref_release_aarch64/lauterbach_R32.3.1_aarch64.tbz2

Yeah we’ve looked at the lauterbach stuff. Its definitely helpful in pointing in the right direction and I’ll be using what I can from it to build my open-ocd configuration. We however don’t have a lauterbach debugger so we’re going to have to setup a config for that.

I have a flyswatter 2, and was not able to get this to work on the older 32-bit TK1. Later I got the Lauterbach Trace32, and had only partial success on TX1 and TX2. Even when I thought it was working I found that anything causing the kernel to fail also crashed the actual debugger, and the Lauterbach tech support was not particularly interested in helping.

Yeah that’s in line with what i’ve read. It seems like I should be able to get the Flyswatter 2 working, but I don’t have enough experience to know one way or another. Do you have any of the configuration you did with the Flyswatter around that you’d be willing to share?

I never got it to work. The experiments I did were from the TK1 long ago, so I don’t really have anything useful. :(

No problem. I appreciate the response. I seem to be making some progress in understanding how to set things up. If i’m successful I’ll publish what I get.

So got a board config and tx2 config sort of working its not 100% there and still looking for guidance if anyone can offer some.

board/nvidia_tx2_developer.cfg

#
# configuration file for nvidia_tx_developer
#

# set a safe JTAG clock speed, can be overridden
adapter speed 5000

# default JTAG configuration has only SRST and no TRST
reset_config srst_only

# delay after SRST goes inactive
adapter srst delay 70

# board has an i.MX8MQ with 4 Cortex-A53 cores
set CHIPNAME jetsontx2
set CHIPCORES 6

# source SoC configuration
source [find target/nvidia_jetsontx2.cfg]

nvidia_jetsontx2.cfg

#
# nvidia JETSON TX2 w/ ARM Cortex-v8
#

if { [info exists CHIPNAME] } {
  set _CHIPNAME $CHIPNAME
} else {
  set _CHIPNAME jetsontx2
}

if { [info exists CHIPCORES] } {
    set _cores $CHIPCORES
} else {
    set _cores 6
}

# CoreSight Debug Access Port
if { [info exists DAP_TAPID] } {
        set _DAP_TAPID $DAP_TAPID
} else {
        set _DAP_TAPID 0x5ba00477
}

# the DAP tap
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0x0f \
        -expected-id $_DAP_TAPID

dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu

set _TARGETNAME $_CHIPNAME.a57
set _CTINAME $_CHIPNAME.cti

set DBGBASE {0x81810000 0x81910000 0x81a10000 0x81b10000 0x81410000 0x81510000}
set CTIBASE {0x81820000 0x81920000 0x81a20000 0x81b20000 0x81420000 0x81520000}

for { set _core 0 } { $_core < $_cores } { incr _core } {

    cti create $_CTINAME.$_core -dap $_CHIPNAME.dap -ap-num 1 \
        -ctibase [lindex $CTIBASE $_core]

    set _command "target create $_TARGETNAME.$_core aarch64 -dap $_CHIPNAME.dap \
        -dbgbase [lindex $DBGBASE $_core] -cti $_CTINAME.$_core"

    if { $_core != 0 } {
        # non-boot core examination may fail
        set _command "$_command -defer-examine"
        set _smp_command "$_smp_command $_TARGETNAME.$_core"
    } else {
        set _smp_command "target smp $_TARGETNAME.$_core"
    }

    eval $_command
}

eval $_smp_command

targets $_TARGETNAME.0

Hi

what do you mean with “working”?
I was not able to stop any core.

Are you sure -ap-num 1 is right and shouldn’t be 0. Because the TRM says:

This means to me you’re using the AXI AP - whcih is not what I expected to work. And I tried myself a lot of debugging - but wasn’t able to stop any core. What I have observed is that dap info doesn’t dump the ROM anymore as expected - why this happens I don’t know yet. Obiviously I also tried -ap-num 1 with the same effect.

once I have executed one target create I think something is stuck - obviously:

tx2.dap info
AP ID register 0x44770002
Type is MEM-AP APB
MEM-AP BASE 0x44770002
No ROM table present
cti0 dump
CTR (0x0000) 0x44770002
GATE (0x0140) 0x44770002
INEN0 (0x0020) 0x44770002
INEN1 (0x0024) 0x44770002
INEN2 (0x0028) 0x44770002
INEN3 (0x002c) 0x44770002
INEN4 (0x0030) 0x44770002
INEN5 (0x0034) 0x44770002
INEN6 (0x0038) 0x44770002
INEN7 (0x003c) 0x44770002
INEN8 (0x0040) 0x44770002
OUTEN0 (0x00a0) 0x44770002
OUTEN1 (0x00a4) 0x44770002
OUTEN2 (0x00a8) 0x44770002
OUTEN3 (0x00ac) 0x44770002
OUTEN4 (0x00b0) 0x44770002
OUTEN5 (0x00b4) 0x44770002
OUTEN6 (0x00b8) 0x44770002
OUTEN7 (0x00bc) 0x44770002
OUTEN8 (0x00c0) 0x44770002
TRIN (0x0130) 0x44770002
TROUT (0x0134) 0x44770002
CHIN (0x0138) 0x44770002
CHOUT (0x013c) 0x44770002
APPSET (0x0014) 0x44770002
APPCLR (0x0018) 0x44770002
APPPULSE (0x001c) 0x44770002
INACK (0x0010) 0x44770002

I have used head revision 8d748f426c7a9c750ffc7cabfbb87bc2cecd82d3 of today - which version did you use?

I would add this mem device to access AXI port
target create _CTINAME.mem mem_ap -dap _CHIPNAME.dap -ap-num 1 -defer-examine

This is for the R5 cores
cti create cti6 -dap _CTINAME.dap -ctibase 0x80a18000 -ap-num 0 target create _CTINAME.r5.0 cortex_r4 -dap $_CHIPNAME.dap -ap-num 0 -dbgbase 0x80a10000 -defer-examine

cti create cti7 -dap _CTINAME.dap -ctibase 0x80b18000 -ap-num 0 target create _CTINAME.r5.1 cortex_r4 -dap $_CHIPNAME.dap -ap-num 0 -dbgbase 0x80b10000 -defer-examine

cti create cti8 -dap _CTINAME.dap -ctibase 0x80c18000 -ap-num 0 target create _CTINAME.r5.2 cortex_r4 -dap $_CHIPNAME.dap -ap-num 0 -dbgbase 0x80c10000 -defer-examine

This is the A9 core
cti create cti9 -dap _CTINAME.dap -ctibase 0x80918000 -ap-num 0 target create _CTINAME.a9.2 cortex_a -dap $_CHIPNAME.dap -ap-num 0 -dbgbase 0x80910000 -defer-examine

But these cores are not detected properly/detected as off - where I doubt that this is linked with the stuck reply you can see in the dumps
I receive:
target->coreid 0 powered down!

Kind Regards
Thorsten