I’m interested in getting the TX2 Dev Kit JTAG working with the TX2 developer kit. Is there anyone that could provide some guidance? Searches have yielded very little information. We have a flyswatter2 debugger which uses open-ocd. From what I can tell it should be possible but no configurations exist for this board/target combo. This would be a very valuable resource for me, and I’m sure it would help others in TX2 development. Just wondering if anyone has had success with anything like this and if anyone is willing to provide guidance/help that they’ve gotten in this area. Thank you.

Have a check the lauterbach.


Yeah we’ve looked at the lauterbach stuff. Its definitely helpful in pointing in the right direction and I’ll be using what I can from it to build my open-ocd configuration. We however don’t have a lauterbach debugger so we’re going to have to setup a config for that.

I have a flyswatter 2, and was not able to get this to work on the older 32-bit TK1. Later I got the Lauterbach Trace32, and had only partial success on TX1 and TX2. Even when I thought it was working I found that anything causing the kernel to fail also crashed the actual debugger, and the Lauterbach tech support was not particularly interested in helping.

Yeah that’s in line with what i’ve read. It seems like I should be able to get the Flyswatter 2 working, but I don’t have enough experience to know one way or another. Do you have any of the configuration you did with the Flyswatter around that you’d be willing to share?

I never got it to work. The experiments I did were from the TK1 long ago, so I don’t really have anything useful. :(

No problem. I appreciate the response. I seem to be making some progress in understanding how to set things up. If i’m successful I’ll publish what I get.

So got a board config and tx2 config sort of working its not 100% there and still looking for guidance if anyone can offer some.


# configuration file for nvidia_tx_developer

# set a safe JTAG clock speed, can be overridden
adapter speed 5000

# default JTAG configuration has only SRST and no TRST
reset_config srst_only

# delay after SRST goes inactive
adapter srst delay 70

# board has an i.MX8MQ with 4 Cortex-A53 cores
set CHIPNAME jetsontx2

# source SoC configuration
source [find target/nvidia_jetsontx2.cfg]


# nvidia JETSON TX2 w/ ARM Cortex-v8

if { [info exists CHIPNAME] } {
} else {
  set _CHIPNAME jetsontx2

if { [info exists CHIPCORES] } {
    set _cores $CHIPCORES
} else {
    set _cores 6

# CoreSight Debug Access Port
if { [info exists DAP_TAPID] } {
        set _DAP_TAPID $DAP_TAPID
} else {
        set _DAP_TAPID 0x5ba00477

# the DAP tap
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0x0f \
        -expected-id $_DAP_TAPID

dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu


set DBGBASE {0x81810000 0x81910000 0x81a10000 0x81b10000 0x81410000 0x81510000}
set CTIBASE {0x81820000 0x81920000 0x81a20000 0x81b20000 0x81420000 0x81520000}

for { set _core 0 } { $_core < $_cores } { incr _core } {

    cti create $_CTINAME.$_core -dap $_CHIPNAME.dap -ap-num 1 \
        -ctibase [lindex $CTIBASE $_core]

    set _command "target create $_TARGETNAME.$_core aarch64 -dap $_CHIPNAME.dap \
        -dbgbase [lindex $DBGBASE $_core] -cti $_CTINAME.$_core"

    if { $_core != 0 } {
        # non-boot core examination may fail
        set _command "$_command -defer-examine"
        set _smp_command "$_smp_command $_TARGETNAME.$_core"
    } else {
        set _smp_command "target smp $_TARGETNAME.$_core"

    eval $_command

eval $_smp_command

targets $_TARGETNAME.0