TX2 NX can't driver SYS_RESET after power down and power on

Hi Nvidias,

we design carrier board colay NX /NANO/TX2 NANO,It can work normal on NX/NANO,but it work abnormal on TX2 NX。 when first power it work normal,but after power off and power on then it can’t work.
we measured VDD_IN is 5V and power_EN is normal 5V level,but SYS_RESET did not driver out High.It looks like the module did not power up itself.
pls give some advices to debug my carrier board.

Please refer to this topic: Announcing Jetson TX2 NX - #3 by XeroX
and below doc in DLC for migration between TX2 NX, Xavier NX and nano.

The TX2 NX driver SYS_RESET is different from NX/NANO.we carrier board have supply 5V VDD_IN and driver High POWER_EN,but SYS_RESET did not driver high.
We check DG show that diver SYS_RESET High need supply 5V VDD_IN and POWER_EN.
There must be some condition force the TX2 NX hold the SYS_RESET,Could you point out why The module hold the SYS_RESET single.
We designed 4 different Carrier board,two of them are work normally and the other two did not.and the 4 carrier board all work normal on NX and NANO.We are confused why TX2 NX have difference behavior.
The power on sequence digrams are same.how can I found the reason that The TX2 NX hold SYS_RESET.

Can the TX2 NX module power on with carrier board of devkit? If not, it might be broken as you said “when first power it work normal,but after power off and power on then it can’t work”

The TX2 NX do once power on and power on then take it on devkit power on,it can not work.we must do once power on and power off,then It can work normal.We want debug why SYS_RESET have hold,we did not know the module design and the DG did not show the condition.
Could you show us the SYS_RESET desgin and PMIC desgin SCH,or show detail condition the modlue will drive High SYS_RESET.

The SYS_RESET is driven by PMIC to indicate power-on sequence finished. If it keeps low always, that means some steps of power-on is not successful. As said, there are some interface difference between TX2 NX, nano and Xavier NX carrier board, you should check your board design not only on power part, but also on all interface to make sure them fit the requests of product design guide, as some violation might cause IO status wrong which might cause power-on fail.

Finally,I found the issue is related to power down sequense.Our carriver board timing between POWER_EN and VDD_IN is more than 100ms and devkit timing is more than 1s。ALl of then meet the timing daigram,but our carrier board can not power up,and I manual driver low the power_EN before power power down and normal power up,In this condtion our carrier board is power up normally.I am confuse with the timing diagram and Did Nvidia have verify the power down timing on TX2 NX module.And what is the
accurate value between Power_EN and VDD_IN.

There is no critical timing request between POWER_EN and VDD_IN. For power-on, POWER_EN should be asserted after VDD_IN is stable. For Power-off, no request. For sudden power loss you posted, it should be >10ms to let system has enough time to run power down sequence.