We’ve been working on using the lt6911uxc to input HDMI video to the TX2 NX.
We cannot capture video with v4l2. We have probed the CSI lines from the lt6911uxc chip and it appears to have data coming out.
Questions:
1) We put in mode info in the DT (Device Tree) and now we see the video input change from HDMI to Cameral when we use ‘v4l2-ctl --all’. Why has the video input changed from HDMI to Camera? I have a Toshiba tc358743 running with and Xavier NX that shows up as HDMI not a camera.
Before:
Video input : 0 (HDMI 0: no signal)
After:
Video input : 0 (Camera 0: no power)
2) We have noticed that the lt6911uxc driver is loaded but it shows up as not being used until we try and capture video with the following. Again, the Toshiba setup shows the driver in use even when video is not being captured. Should the driver be in use?
3) When trying to capture video the v4l2-ctl command just hangs trying to capture video and produces these repeating errors in dmesg:
Nov 3 16:27:23 ams1pdev5 kernel: [ 2666.220223] tegra-vi4 [15700000.vi](http://15700000.vi/): PXL_SOF syncpt timeout! err = -11
Nov 3 16:27:23 ams1pdev5 kernel: [ 2666.226739] tegra-vi4 [15700000.vi](http://15700000.vi/): tegra_channel_error_recovery: attempting to reset the
4) Is anyone using the Lontium dev/evk board and wiring the CSI lines to a carrier board? If so is there a particular carrier board that exposes all 4 lines on each CSI port of the SoM? We tried using the Xavier NX Dev board but the carrier board only exposes 2 lines. In theory we only need this for 4kp60 but part of what we are trying to do is prove the lt6911uxc is capable of capturing 4kp60. At this point however if we could do 4kp30 with 1 lane I’d be happy. Heck, I’d even take 480i just to prove that we get something.
>> Q1
please check Kconfig, you may modify that similar to Toshiba bridge driver for confirmation.
>> Q2
may I know what’s the sources of this lt6911uxc bridge? or, had you enable test-pattern-generator?
>> Q3
can you confirm there’s signaling sending to CSI brick?
this error log PXL_SOF, it means VI engine cannot receive start-of-frame correctly.
it may due to you’ve longer initial time then the timeout limit, i.e. 2500ms.
please add set_mode_delay_ms DT settings to configure wait time for the first frame after capture starts, the unit is in milliseconds.
>> Q4
I am not quite understand this part.
there’s lane configuration in device tree, which correspond to the actual hardware settings.
for example, if your bridge used 4-lane, you need to configure bus-width = <4>.
moreover, for TX2 series, due to the bandwidth, you should enable 8-lane to bring-up 4kp60.
Q1
This is what I’ve got for the lt6911uxc in /Linux_for_Tegra/source/public/kernel/nvidia/drivers/media/i2c/Kconfig
config VIDEO_LT6911UXC
tristate "Lontium LTX6911UXC HDMI to CSI bridge"
depends on VIDEO_V4L2 && VIDEO_V4L2_SUBDEV_API
---help---
This driver supports LT6911UXC bridge from Lontium
To compile this driver as a module, choose M here: the module
will be called lt6911uxc.
For the Toshiba the Kconfig is over here :
/Linux_for_Tegra/source/public/kernel/kernel-4.9/drivers/media/i2c/Kconfig
config VIDEO_TC358743
tristate "Toshiba TC358743 decoder"
depends on VIDEO_V4L2 && I2C && VIDEO_V4L2_SUBDEV_API
select HDMI
---help---
Support for the Toshiba TC358743 HDMI to MIPI CSI-2 bridge.
To compile this driver as a module, choose M here: the
module will be called tc358743.
So we would add the “select HDMI” in the Lontium section and re-make the kernel first re-running “menuconfig”?
In order for it to work correctly do we need to add this or does it matter?
Q2
We are using a TV set top box as the source video. It is not using HDCP. It is the same source we are using with the Toshiba chip/bridge.
Q3
How exactly can we confirm the signaling to the CSI brick? We have probed the CSI lines coming from the Lontium chip and can verify there is a signal.
Would we set the 'set_mode_delay_ms` in the the VI section of the DT or somewhere else?
Q4.
This is good information. The way we understand it the TX2 has 2 CSI ports and each port has 4 CSI lanes. This would give us the 8 we need for 4kp60. We also understand there is a clock tied to each CSI port. In order to use all 8 lanes we have to use one clock for both ports. How is this set?
Also, the Lontium firmware is configured to use 1 port ( 4 CSI lanes) for 4kp30 and below. If it is 4kp60 it will use 2 ports ( 8 CSI lanes). Is this possible to configure so that we can switch between resolutions?
Our first step is to verify the Lontium chip is capable of ingesting video.
Second we need to verify the Lontium chip is capable of ingesting 4kp60 video.
We have been unable to do either of these steps. Part of our problem is we are working with a newly developed carrier board for the SOM that integrates the Lontium chip in the design. We would love to first work with a known hardware platform e.g. an Nvidia Dev Kit with a dev board from Lontium in order to prove out the solution but nothing seems to exist. Please share if you know of something that exists. A platform must exist as something was used to develop the Nvidia driver for the Lontium chip.
one CSI brick capable to 1-lane, 2-lane, and 4-lane.
there’s gang mode mechanism, (for only 4k resolutions). if you assign bus-width = <8>; in device tree. VI driver will enable two CSI bricks to handle the signaling. these must be continuous 8-lanes configuration. for example, CSI-A,B/CSI-C,D.
you may dig into VI driver for gang mode implementation.
for example, $public_sources/kernel_src/kernel/nvidia/drivers/media/platform/tegra/camera/vi/channel.c
this looks promising.
so, basically, you’ll need to configure device tree as same as hardware config.
you should have correct port bindings. please see-also bridge driver, tc358840 for reference.
VI tracing log it helps to dig into the issue.
here’re steps to enable that, please share VI tracing logs for reference if Tegra side still not receiving the signaling.
for example,
Q2
Made the change in the DT but haven’t seen any difference.
Q3
We have gotten new information from Lontium that 4kp60 4:2:2 can be done with 1 CSI port and 4 lanes. They have said the FW needs to be set up correctly so working with them to provide a new FW after we clarify our 4kp60 is in a 4:2:2 color space
@JerryChang
Thanks for taking a look at these errors!
The Lontium chip has FW that is loaded on the chip. I’m wondering if the mismatch is occurring due to incorrect FW for the settings we have in the DT.
The current FW we are using indicates RGB444. We do have another FW that is setup for YUV422.
Do you know if this is the pixel_phase attribute in the DT?
Our dtsi file is set to: pixel_phase = “rggb”;
As a reference my dtsi file for the Toshiba chip does not have a pixel_phase set. We are using the Nvidia Lontium driver. Maybe it’s a setting the particular driver needs set?
what’s the pixel formats sending to CSI brick, it should be YUV, right?
actually, you may refer to Toshiba driver to leave only port bindings in device tree.