TX2 (p3310) UART configuration

Hi @JerryChang
thanks for your reply.
according to Jetson TX2 Series OEM Product Design Guide, UART7 physical connections are confirmed well.
and we tried the methord in this post, but it seemed no help.
how to verify that tegra186-a02-bpmp-quill-p3310-1000-c04-00-te770d-ucm2.dtb has been updated in our device? is there any log?

now, the uart0 uart1 and uart2 work well. we tested in the following methord.
echo “uart0 test” > /dev/ttyS0 signal cought on uart0
echo “uart1 test” > /dev/ttyTHS2 signal cought on uart1
echo “uart2 test” > /dev/ttyTHS3 signal cought on uart2
is this mapping right?
should uart7 be mapped to ttyTHS8?
Regards

hello Henry.Lou,

please check kernel logs for the UART mappings, i.e. $ dmesg | grep THS

Hi @JerryChang
We modified DT, and now /dev/ttyTHS6 came out. We also did some tests.
signals can be cought on UART7, however, UART3 still does not work.
what`s more, the mapping between UART and tty changed.
the test results are shown as following.

echo “uart0 test” > /dev/ttyS0 signal cought on uart0
echo “uart1 test” > /dev/ttyTHS2 signal cought on uart1
echo “uart2 test” > /dev/ttyTHS1 signal cought on uart2
echo “uart7 test” > /dev/ttyTHS6 signal cought on uart7

the UART1 works at 9600 baud rate, we expect to change it to 115200. could you give some suggestions?

Regards
FYI

t@t-desktop:~$ dmesg | grep "TH"
[    3.473637] 3110000.serial: ttyTHS1 at MMIO 0x3110000 (irq = 37, base_baud = 0) is a TEGRA_UART
[    3.474535] c280000.serial: ttyTHS2 at MMIO 0xc280000 (irq = 38, base_baud = 0) is a TEGRA_UART
[    3.475507] 3130000.serial: ttyTHS3 at MMIO 0x3130000 (irq = 39, base_baud = 0) is a TEGRA_UART
[    3.476387] c290000.serial: ttyTHS6 at MMIO 0xc290000 (irq = 40, base_baud = 0) is a TEGRA_UART
[    3.488627] THERMAL EST: found 3 subdevs
[    3.488630] THERMAL EST num_resources: 0
[    3.488633] [THERMAL EST subdev 0]
[    3.488637] [THERMAL EST subdev 1]
[    3.488640] [THERMAL EST subdev 2]
[    3.488903] THERMAL EST: thz register success.
[    3.488994] THERMAL EST: end of probe, return err: 0
[    7.308526] systemd[1]: Proceeding WITHOUT firewalling in effect! (This warning is only shown for the first loaded unit using IP firewalling.)
[   29.333012] [08-08 05:09:52.533] dhd_dump_eapol_4way_message: ifidx: 0 ETHER_TYPE_802_1X [RX] : M1 of 4way
[   29.340938] [08-08 05:09:52.541] dhd_dump_eapol_4way_message: ifidx: 0 ETHER_TYPE_802_1X [TX] : M2 of 4way
[   29.346410] [08-08 05:09:52.546] dhd_dump_eapol_4way_message: ifidx: 0 ETHER_TYPE_802_1X [RX] : M3 of 4way
[   29.346591] [08-08 05:09:52.546] dhd_dump_eapol_4way_message: ifidx: 0 ETHER_TYPE_802_1X [TX] : M4 of 4way

t@t-desktop:~$ ls -ahl /dev/ttyTH*
-rw-r--r-- 1 root root        30 Aug  8 02:59 /dev/ttyTHS0
crw-rw---- 1 root dialout 238, 1 Aug  8 04:02 /dev/ttyTHS1
crw-rw---- 1 root dialout 238, 2 Aug  8 03:39 /dev/ttyTHS2
crw-rw---- 1 root dialout 238, 3 Aug  8 03:58 /dev/ttyTHS3
crw-rw---- 1 root dialout 238, 6 Aug  8 03:59 /dev/ttyTHS6

attachment is the whole dmesg log.
henry7.log (84.2 KB)

hello Henry.Lou,

you meant pin# D9,D10, the serial port header? if yes, it’s UART-C, serial@c280000

Hi @JerryChang
the uart number are based on “SoM connector” in Jetson-TX2-Series-Pinmux-Template_v1.08.xlsm file. We tried to upload the xlsm, but failed. You may get it from the download center.

UART3 is pin# H9, H10. according to the dmesg, it seems that UART3 is UART-d, serial@3130000. and UART3 has been mapped to ttyTHS3. but, it does not work.
echo “uart3 test” > /dev/ttyTHS3 no signal cought on uart3

and what`s more serious, DT has configed UART1 to 115200 baud rate, but it works at 9600 in fact. could you give some help on it.

for UART-D
there’s Mux for UART-3, pin# H9, H10, which choosing WiFi/BT or UART on Jetson TX2.

for UART-A
that’s uarta for the default debug port, you’ll need modifications to treat it as normal serial port. please see-also Topic 199133 for an example to configure debug port from UART-0 to UART-1.

Hi @JerryChang
UART0 used for debug port
UART1 used for common serial port.
That`s fit for our projects.

But, the questions are: in the tegra186-soc-uart.dtsi file, baud rate has been set to 115200. why it works at 9600 in fact?

uartd: serial@c280000 {
compatible = “nvidia,tegra186-hsuart”;
iommus = <&summu TEGRA_SID_GPCDMA_0>;
reg = <0x0 0xc280000 0x0 0x40>;
reg-shift = <2>;
interrupts = <0 TEGRA186_IRQ_UARTD 0x04>;
nvidia,memory-clients = <14>;
dmas = <&gpcdma 3>, <&gpcdma 3>;
dma-names = “rx”, “tx”;
clocks = <&tegra_car TEGRA186_CLK_UARTD>,
<&tegra_car TEGRA186_CLK_PLLP_OUT0>;
clock-names = “serial”, “parent”;
resets = <&tegra_car TEGRA186_RESET_UARTD>;
reset-names = “serial”;
status = “disabled”;
nvidia,adjust-baud-rates = <115200 115200 100>;
};

hello Henry.Lou,

may I know what’s the failure you seen, could you please share some errors for reference.

Hi @JerryChang
OK, let me explain it.
On a windows test PC, we use a USB-RS232(ch340) tool connect the xshell and UART1.
Then, open a terminal on TX2.
echo “uart1 test” > /dev/ttyTHS2
xshell can get the strings only when we set baud rate to 9600.
and no errors print on screen.

hello Henry.Lou,

is this due to configuration issue? please see-also Topic 201881 for reference, thanks

Hi @JerryChang
This topic 201881 realy works and helps us a lot. But, stty command can change baud rate temporarily. If we reboot tx2 baud rate will go back to 9600. So, we need config it when uart init. Could you give some suggestions?

We are so confused that baud rate has been setted to 115200, why it does not work?

Hi @JerryChang
We debuged in the following file.
kernel/kernel-4.9/drivers/tty/serial/serial-tegra.c
Found that, the function tegra_uart_starup() and tegra_uart_hw_init() were never invoked.
So that, the baud rate was not setted.

hello Henry.Lou,

could you please also check below, it should be tegra_uart_parse_dt for reading device tree property, nvidia,adjust-baud-rates and return the values,
could you please check it’s reading correctly?

static int tegra_uart_probe(struct platform_device *pdev)
  	...
  	ret = tegra_uart_parse_dt(pdev, tup);

Hi @JerryChang
We debuged function tegra_uart_parse_dt(), DT has been parsed well.

[    3.479955] (NULL device *): henry debug tegra_uart_probe line==1838
[    3.479961] serial-tegra 3110000.serial: henry debug tegra_uart_parse_dt entry
[    3.479976] serial-tegra 3110000.serial: henry debug tegra_uart_parse_dt 1685; pval==115200, n_entries==3
[    3.479979] serial-tegra 3110000.serial: henry debug tegra_uart_parse_dt 1690; pval==115200
[    3.479983] serial-tegra 3110000.serial: henry debug tegra_uart_parse_dt 1695; pval==100
[    3.479985] serial-tegra 3110000.serial: henry debug tegra_uart_parse_dt leave
[    3.480806] 3110000.serial: ttyTHS1 at MMIO 0x3110000 (irq = 37, base_baud = 0) is a TEGRA_UART
[    3.480989] (NULL device *): henry debug tegra_uart_probe line==1838
[    3.480994] serial-tegra c280000.serial: henry debug tegra_uart_parse_dt entry
[    3.481006] serial-tegra c280000.serial: henry debug tegra_uart_parse_dt 1685; pval==115200, n_entries==3
[    3.481009] serial-tegra c280000.serial: henry debug tegra_uart_parse_dt 1690; pval==115200
[    3.481012] serial-tegra c280000.serial: henry debug tegra_uart_parse_dt 1695; pval==100
[    3.481015] serial-tegra c280000.serial: henry debug tegra_uart_parse_dt leave
[    3.481187] tegra-pcie 10003000.pcie-controller: PCIE: no end points detected
[    3.481521] tegra-pcie 10003000.pcie-controller: PCIE: Disable power rails
[    3.481914] c280000.serial: ttyTHS2 at MMIO 0xc280000 (irq = 38, base_baud = 0) is a TEGRA_UART
[    3.482144] (NULL device *): henry debug tegra_uart_probe line==1838
[    3.482150] serial-tegra 3130000.serial: henry debug tegra_uart_parse_dt entry
[    3.482162] serial-tegra 3130000.serial: henry debug tegra_uart_parse_dt 1685; pval==115200, n_entries==3
[    3.482166] serial-tegra 3130000.serial: henry debug tegra_uart_parse_dt 1690; pval==115200
[    3.482170] serial-tegra 3130000.serial: henry debug tegra_uart_parse_dt 1695; pval==100
[    3.482173] serial-tegra 3130000.serial: henry debug tegra_uart_parse_dt leave
[    3.482937] 3130000.serial: ttyTHS3 at MMIO 0x3130000 (irq = 39, base_baud = 0) is a TEGRA_UART
[    3.483095] (NULL device *): henry debug tegra_uart_probe line==1838
[    3.483100] serial-tegra c290000.serial: henry debug tegra_uart_parse_dt entry
[    3.483112] serial-tegra c290000.serial: henry debug tegra_uart_parse_dt 1685; pval==115200, n_entries==3
[    3.483115] serial-tegra c290000.serial: henry debug tegra_uart_parse_dt 1690; pval==115200
[    3.483119] serial-tegra c290000.serial: henry debug tegra_uart_parse_dt 1695; pval==100
[    3.483121] serial-tegra c290000.serial: henry debug tegra_uart_parse_dt leave
[    3.483829] c290000.serial: ttyTHS6 at MMIO 0xc290000 (irq = 40, base_baud = 0) is a TEGRA_UART

hello Henry.Lou,

driver side looks work normally, it should be system level configuration to overwrite the settings.

Hi @JerryChang
We expect to set baud to a fixed 115200.
and how to change system level configuration, could you give more details?

hello Henry.Lou,

you may have init script file to have stty command for changing baud rate settings.

Hi @JerryChang
where should we locate the init script to make sure change baud rate every time when tx2 bring up?
could you give some examples or demos?

hello Henry.Lou,

please enter /etc/systemd/, you may modify nvgetty.sh for adding configurations.

Hi @JerryChang
We added configuration in the nvgetty.sh on the host pc, and used “flash -r -k kernel jetson-tx2 mmcblk0p1”. But, when device brought up, the script did not chang. Could you give the right command to flash?