What is the driver type (HCSL?) and electrical and jitter characteristics of the TX2 PEX*_REFCLK+/– outputs? I can’t find a description in the datasheet or OEM guide and don’t see a statement as to a reference PCI-SIG specification to refer to.
Thanks!
Hi radeng, did you met any issue? The pin type is PCIe PHY as listed in guide and it is common as other standard PCIe port.
I have yet to get the IBIS models with external spice references to output anything in Hyperlynx. The IBIS and IBIS-AMI models are working great. I was just going to simulate the clock with a generic model and thus would like more information on the electrical signaling type of the REFCLK.
In regard to the PCIe simulations, the total jitter in the link plays a role in the margin of the link. I have yet to be able to find a jitter specifications in the documentation of the PEX REFCLK outputs or any information on the additive jitter of the TX2 transmitter or receiver. Any information in this regard would help add confidence to the overall PCIe simulation.
In general do the S-parameters include or exclude the Samtec connector on the TX2 module or only U3 and the module PCB? I wasn’t clear from the description in the model, exactly was portion of the module included in the measurement of the S-parameter model. I have been assuming the models provided included represent the entire module and the only additional model I need to add to our carrier board is the s-parameter model for the mating Samtec SEAM connector of the carrier that mates to the TX2 module.
Thanks!
Assume you already checked the S-Parameter and IBIS Models in DLC, right? It is for the module. And what we can provide are all in DLC, no other doc is available.
Trumany,
I have the latest models. In general for the S-parameters included what portion of the module do they reflect? PCB only, PCB and J501, etc. Where was the probe points for the measurements that produced these S-parameters or what is the de-embedded portion of the module and connectors these represent?
Thanks,
radeng