I have a doubt regarding the role of the RESET_IN# signal (if any) on the power up sequence of TX2. According to the OEM reference manual for P2597 dev kit, the RESET_OUT# signal is held active(low) by the carrier board (by connecting it to the PG of the 1V8 regulator), thus reseting the Tegra and eMMC, preventing the system to boot until the carrier 1V8 are stable, then RESET_OUT# goes high.
What is the behaviour of RESET_IN# during this power up sequence? It is not shown in timing diagram of figure 8, but table 7 states that its active time is 50ms. Does it mean it goes from its POR state (pulled up) to active during 50ms and then its de-asserted again?
I am asking because we are implementing an auto-recovery mode circuitry that reproduces the recovery mode sequence after power up is completed. (held FORCE_RECOVERY# low, the assert and de-assert RESET_IN# and then after 2 seconds release FORCE_RECOVERY#). We have seen that, with the dev kit, if you power up the system with the recovery button pressed, it boots in recovery mode. Does that mean the RESET_IN# is generating the required negative pulse, somehow from the power up system?
Could you please provide waveform of the RESET_IN# during power up? Or could you explain why this could happen? Maybe the activation and deactivation of RESET_OUT# during power up is recognised as a reset pulse and thus system goes into recovery mode ?