TX2 SPI 3-wire mode disabled?

Hello, I am currently working on a custom carrier board for the TX2. Part of that board involves a chip that is hooked up via SPI (i.e., a SPI slave device). We are experiencing/debugging some issues on our MISO line, but it seems like writes to the SPI device are working and we have verified that the clock, chip select, and MOSI lines all show the correct data on a scope.

As a result of our MISO line issues (we’re still tracking down what’s going on) we attempted to put everything into 3-wire mode and simply have the SPI slave send it’s data back out over MOSI. However, we encountered an error with the driver stating that 3-wire mode is not supported (I’m paraphrasing the error message I saw in dmesg).

Looking at the code, (namely kernel/kernel-4.4/drivers/spi/spi-tegra114.c from the 28.2.1 source), it seems like the flag for 3-wire is not included in the mode_bits. I have reproduced lines 1901-1903 from spi-tegra114.c below:

/* the spi->mode bits understood by this driver: */
	master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST |
		SPI_TX_DUAL | SPI_RX_DUAL | SPI_LSBYTE_FIRST;

I’m wondering if the lack of SPI_3WIRE was just an oversight or done intentionally. Will I break anything if I add SPI_3WIRE to the mode_bits and re-compile the kernel? Is 3-wire mode supported? I’m assuming I have to re-build the kernel since it appears that this driver is baked into the kernel itself and is not a module.

@dwd_pete

Nothing will be broken by enabling SPI 3-WIRE.

MISO not working could be a pinmux issues.

My problems with reads were caused by a bug that was injected when spidev.c was “fixed” for the Tegra. Based on how the rx_buf is advanced even if you are only doing a TX, I’m assuming I would of had the same issue with 3-wire mode.

https://devtalk.nvidia.com/default/topic/1044272/jetson-tx2/tx2-spi-half-duplex-transfers-broken/