TX2 VI4 master error debug

Arun_work · February 6, 2018, 4:01pm

Hi,

Could you clarify when do we get ‘master error’.

...
[  174.263988] tegra-vi4 15700000.vi: master error
[  174.274956] tegra-vi4 15700000.vi: master error
[  174.285918] tegra-vi4 15700000.vi: master error
[  174.296880] tegra-vi4 15700000.vi: master error
[  174.302167] tegra-vi4 15700000.vi: PXL_SOF syncpt timeout! err = -11

I am interfacing a CSI2 camera with TX2 using 4 lanes (raw data format). There is data coming up on the lanes.

I have enabled trace and below are those logs,

kworker/0:0-4     [000] ...1   210.902092: rtos_queue_peek_from_isr_failed: tstamp:6894680886 queue:0x0b4a3c58
     kworker/0:0-4     [000] ...1   210.902096: rtcpu_start: tstamp:6894681850
     kworker/0:0-4     [000] ...1   211.062085: rtos_queue_peek_from_isr_failed: tstamp:6899681728 queue:0x0b4a3c58
     kworker/0:0-4     [000] ...1   211.231902: rtos_queue_peek_from_isr_failed: tstamp:6904682226 queue:0x0b4a3c58
     kworker/0:0-4     [000] ...1   211.394819: rtos_queue_peek_from_isr_failed: tstamp:6909682735 queue:0x0b4a3c58
     kworker/0:0-4     [000] ...1   211.394822: rtcpu_vinotify_handle_msg: tstamp:6909907560 tag:CSIMUX_STREAM channel:0xff frame:0 vi_tstamp:2614939845 data:0x00010000
     kworker/0:0-4     [000] ...1   211.394823: rtcpu_vinotify_handle_msg: tstamp:6910005707 tag:CSIMUX_STREAM channel:0xff frame:0 vi_tstamp:2615037997 data:0x00020000
     kworker/0:0-4     [000] ...1   211.447109: rtcpu_vinotify_handle_msg: tstamp:6910348354 tag:CSIMUX_STREAM channel:0xff frame:0 vi_tstamp:2615380519 data:0x00040000
     kworker/0:0-4     [000] ...1   211.447110: rtcpu_vinotify_handle_msg: tstamp:6910348542 tag:CSIMUX_STREAM channel:0xff frame:0 vi_tstamp:2615380549 data:0x00020000
     kworker/0:0-4     [000] ...1   211.447111: rtcpu_vinotify_handle_msg: tstamp:6910690976 tag:CSIMUX_STREAM channel:0xff frame:0 vi_tstamp:2615723142 data:0x00040000
     kworker/0:0-4     [000] ...1   211.447112: rtcpu_vinotify_handle_msg: tstamp:6910691164 tag:CSIMUX_STREAM channel:0xff frame:0 vi_tstamp:2615723172 data:0x00020000
     kworker/0:0-4     [000] ...1   211.447113: rtcpu_vinotify_handle_msg: tstamp:6911033599 tag:CSIMUX_STREAM channel:0xff frame:0 vi_tstamp:2616065763 data:0x00040000
     kworker/0:0-4     [000] ...1   211.447113: rtcpu_vinotify_handle_msg: tstamp:6911033787 tag:CSIMUX_STREAM channel:0xff frame:0 vi_tstamp:2616065793 data:0x00020000
     kworker/0:0-4     [000] ...1   211.447114: rtcpu_vinotify_handle_msg: tstamp:6911376217 tag:CSIMUX_STREAM channel:0xff frame:0 vi_tstamp:2616408386 data:0x00040000
     kworker/0:0-4     [000] ...1   211.447115: rtcpu_vinotify_handle_msg: tstamp:6911376405 tag:CSIMUX_STREAM channel:0xff frame:0 vi_tstamp:2616408416 data:0x00020000
     kworker/0:0-4     [000] ...1   211.447116: rtcpu_vinotify_handle_msg: tstamp:6911718842 tag:CSIMUX_STREAM channel:0xff frame:0 vi_tstamp:2616751008 data:0x00040000
     kworker/0:0-4     [000] ...1   211.447116: rtcpu_vinotify_handle_msg: tstamp:6911719029 tag:CSIMUX_STREAM channel:0xff frame:0 vi_tstamp:2616751038 data:0x00020000
     kworker/0:0-4     [000] ...1   211.501948: rtcpu_vinotify_handle_msg: tstamp:6912061466 tag:CSIMUX_STREAM channel:0xff frame:0 vi_tstamp:2617093630 data:0x00040000

One of the post mentions that it is due to Clock mismatch between VI and ISP interfaces but doesn’t provide more details.

trace msgs are from CSIMUX which is the frontend of VI so the data hasn’t passed through VI yet so wondering how it can be a clock mismatch between VI and ISP (as ISP comes after VI)?

CSIMUX_STREAM is also an error event but it is not clear to me how to interpret the ‘data’ field in the msg.
Does this channel specify the channel id in the VI? I believe there are only 12 channels so 0xff seems incorrect. Could it be why I am hitting this error?

Please let me know what does this error indicate.

Arun_work · February 7, 2018, 4:56pm

I am also seeing MASTER_ERROR_STATUS log entry sometimes,

[   59.646478] tegra-vi4 15700000.vi: master error
[   59.662149] tegra-vi4 15700000.vi: PXL_SOF syncpt timeout! err = -11
[   59.668590] tegra-vi4 15700000.vi: VI_CFG_INTERRUPT_STATUS_0: MASTER_ERR_STATUS error!
[   59.668595] tegra-vi4 15700000.vi: master error

And CFG_INTERRUPT_MASK is set to 0xf9 so it is possible that it could be CSIMUX_FIFO_OVFL_ERR ?

If it is a overflow error then probably input rate is higher than readout rate or nothing is being readout (into VI) but it is not clear how to debug further.

Could you provide any clarifications on this?

JerryChang · February 8, 2018, 9:27am

hel,lo Arun_work,

please check [Release 28.1 Development Guide]-> [Camera Development]-> [Sensor Driver Programming Guide]-> [Debugging Tips]
also, there’s external wiki page for your reference. [url]https://elinux.org/Jetson_TX2/28.1_Camera_BringUp[/url]
thanks

Arun_work · February 8, 2018, 9:34am

Hi Jerry,

Yes, I have already checked that page and enabled trace.
Also it is not an actual camera, we are using Parallel-CSI2 bridge and there is no metadata.
I have not included ‘embedded_metadata_height’ in the device tree but I can set to zero and see if it helps.

I am interested to know when we can hit ‘master error’ and what might be happening at the CSI Rx side which is reporting this error.

regards

Arun_work · February 8, 2018, 5:23pm

@JerryChang,

I found some additional details in the Parker TRM.

"It is an error for any NOTIFY FIFO (either a source FIFO, or a CPU buffer FIFO) to overflow; this error is signaled by setting the NOTIFY_FIFO_OVERFLOW bit in the VI master error register, which triggers a VI master error interrupt as a result

NOTIFY_FIFO_OVERFLOW: Set by Hardware when any of the NOTIFY input FIFO has overflowed. This basically means that Real Time CPU has not been able to keep up its pace with the notify events arrival speed. Write 1 to clear. Also causes VI Master error.
"

Another possibility is,
VI_ISPBUFA_ERROR_0 register:
FIFO_OVERFLOW: Set by Hardware when the ISPBUF’s internal FIFO has overflowed. (Generally due to clock speed mismatch b/w ISP and VI interfaces) Write 1 to clear. Also causes VI Master error.

In our case PXL_SOF is not received yet, so my understanding is that data hasn’t reached ISP in the pipeline (also I am doing a raw capture) so the master error is mostly because of NOTIFY_FIFO_OVERFLOW.

Now the question is why the FIFO is overflowing.

either RTCPU not reading or not at a sufficient rate
errors being generated at a higher rate

RTCPU configuration is not touched and I can stream video with Jetson board camera module so most likely reason is that errors being generated at higher rate?

Any suggestions on what could be the possible reasons?
Since the data reached up to CSIMUX, does this confirm that MIPI timing from Tx matches at receiver end?

JerryChang · February 9, 2018, 8:25am

hello Arun_work,

since you’re using Parallel-CSI2 bridge, are you able to generate the test-pattern for verification?
thanks

Arun_work · February 9, 2018, 8:42am

Hi JerryChang,

Yes, I forgot to mention this is with the test pattern data coming out from Parallel-CSI2 bridge IC.

regards
Arun

Arun_work · February 9, 2018, 4:31pm

I am able to capture the test pattern data from the Parallel-CSI2 bridge, this can be closed now.

JerryChang · February 12, 2018, 1:47am

hello Arun_work,

good to know that works.

before we close the issue.
could you share the finding/ modification you have done to us.
thanks

Arun_work · February 12, 2018, 9:00am

This was a change on our side, one of the register didn’t get programmed correctly.

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TX2 VI4 master error debug

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