TX2i + xilinx K7 FPGA PCIex4 Error

Hi
1、Currently, our architecture is xilinx K7 FPGA connected to TX2 through PCIEX4.TX2 is the root, and the FPGA is the endpoint.PCIE’s error checking is accidental, and sometimes the system calls decoding error when it comes to power, which is normal in most cases.Under normal conditions, PCIE works steadily all the time.Every time a problem occurs, it occurs during the startup phase.
**The attached pcie_err.txt file is the PCIE error log information.The attached pcie_noerr.txt file is the log information that works normally
2、Are there any sequential requirements for FPGA startup and TX2 startup as well as any special requirements for wake signal and CLKREQ signal?
**The attached Sch.jpg file is the design of the PCIE part of our schematic diagram
pci_err.txt (5.6 KB) pci_noerr.txt (2.3 KB)

Is it possible that the FPGA endpoint is not ready by the time Tegra start communicating with FPGA endpoint? Although that shouldn’t result in this kind of error, just to rule that out, can we add some delay post PCIe link up to see if that resolves the issue?

According to you, how do we add latency at startup to wait for the FPGA device? thank you

The following patch can be applied (play around with the time to increase the delay)

diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c
index 7b6fbd5d90a8..d189348fddcd 100644
--- a/drivers/pci/host/pci-tegra.c
+++ b/drivers/pci/host/pci-tegra.c
@@ -2513,6 +2513,7 @@ static void tegra_pcie_check_ports(struct tegra_pcie *pcie)
        }
 
        /* Wait for clock to latch (min of 100us) */
+       msleep(10000);  /* currently it is 10 sec. Adjust here to increase/decrease it */
        udelay(100);
        reset_control_deassert(pcie->pciex_rst);
        /* at this point in time, there is no end point which would