I’m working on a replacement kernel that’s running at EL1 on the TX2. It runs via u-boot, booting into EL2 then quickly switching to EL1. The problem I am running into is enabling UARTA interrupts. Specifically, I can’t get the board to respond to uart RXD (received data) interrupts. Right now the kernel runs exclusively on core 0 of the Cortex A-57.
Steps I’m taking:
- Enabling interrupt 0d144 in the GIC-400.
- Writing 0x01 to the UART_IER register. This enables the RXD interrupt for the 16550. (When received data is available, an interrupt should be asserted to the interrupt controller).
- Input a character to UARTA.
I’m using GICD_BASE==0x03881000u, UARTA_BASE==0x03100000. UARTA should be (in the GIC) interrupt 0d144. The interrupt map in the TX2 TRM shows that UARTA’s interrupt is 0d112 in the LIC, which maps 32 higher once it gets to the GIC-400.
I thought this might be a problem with interrupt groups, but communication through the same UART works just fine during U-Boot (at EL2, already non-secure), and with the prepackaged linux kernel.
I also know that my code / the GIC-400 are working correctly, because my code successfully takes/handles system calls from EL0, as well as timer interrupts via the generic timer.
Other constants: UART_IER = 0x4
I’m somewhat of a baremetal programming novice, so there’s probably something obvious I’m missing here.