We are currently designing an AGX Xavier Carrier Board. I wanted to ask some questions.
The Schematic checklist mentions pulling up RX line of Debug UART by 10k after level translator to translated voltage. Whereas, according to OEM guide DG-09840-001_v2.4, Figure 15-2 shows pull down by 100k on RX line. Similarly RX line is pulled down in Carrier Board Schematic before U60 buffer. My assumptions is that if the intention is to prevent it from floating both options will work provided that the interfacing devices are voltage tolerant to pull up voltage. Am I assuming this correct?
we possibly intend to implement RS-232 on UART 1 and UART 3. To meet strapping pin requirements for UART1_TX, we intend to use a GPIO towards the transceiver to enable and disable it and thus allowing High-Z state on UART lines on boot process. Will this potentially be causing an issue for Debug UART (3) in the initial boot or not?