# UART1 HW flowcontrol behavior is abnormal

**URL:** <https://forums.developer.nvidia.com/t/uart1-hw-flowcontrol-behavior-is-abnormal/270358>\
**Category:** Jetson Orin Nano\
**Tags:** uart, board-design\
**Created:** [October 23, 2023, 10:45am UTC](https://forums.developer.nvidia.com/t/uart1-hw-flowcontrol-behavior-is-abnormal/270358 "2023-10-23T10:45:40Z")\
**Posts on this page:** 5\
**Page:** 1

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**Author:** ![myers](https://developer.download.nvidia.com/images/forums/profile-default-devtalk-84.png) [@myers](https://forums.developer.nvidia.com/u/myers)\
**Post date:** [October 23, 2023, 10:45am UTC](https://forums.developer.nvidia.com/t/uart1-hw-flowcontrol-behavior-is-abnormal/270358/1 "2023-10-23T10:45:40Z")

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I’m testing the UART1 function. I enable the RTS and CTS of UART1 and connect Orin NANO UART1\_TXD to UART1\_RXD.

 ![image](https://global.discourse-cdn.com/nvidia/original/4X/e/9/0/e9060d3024c2dbf4543e8975f39f372dffda1ca0.png)  
UART1\_RTS and UART1\_CTS is disconnected and use minicom (hw flow control is enabled) to test th uart function.

```auto
sudo minicom -D /dev/ttyTHS0 115200

```

When UART1\_RTS and UART1\_CTS is disconnected, it still can transfer R/W data successfully. Is the behaviour correct?

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**Author:** ![KevinFFF](https://sea2.discourse-cdn.com/nvidia/user_avatar/forums.developer.nvidia.com/kevinfff/32/15508_2.png) [@KevinFFF](https://forums.developer.nvidia.com/u/KevinFFF)\
**Post date:** [October 24, 2023, 2:31am UTC](https://forums.developer.nvidia.com/t/uart1-hw-flowcontrol-behavior-is-abnormal/270358/3 "2023-10-24T02:31:19Z")

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Hi myers,

Are you using the devkit or custom board for Orin Nano?  
What’s your Jetpack version in use?

What’s you UART device connected to your Orin Nano?

> [@myers](#):
>
> When UART1\_RTS and UART1\_CTS is disconnected, it still can transfer R/W data successfully. Is the behaviour correct?

Yes, it seems expected that RTS/CTS will only be used when the RX buffer is full.

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<div class="post-metadata">

**Author:** ![myers](https://developer.download.nvidia.com/images/forums/profile-default-devtalk-84.png) [@myers](https://forums.developer.nvidia.com/u/myers)\
**Post date:** [October 24, 2023, 3:12am UTC](https://forums.developer.nvidia.com/t/uart1-hw-flowcontrol-behavior-is-abnormal/270358/4 "2023-10-24T03:12:44Z")

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Hi KevinFFF,

I use custom board and Jetpack version is 5.1.2. I connect the UART to itself.

 ![image](https://global.discourse-cdn.com/nvidia/original/4X/c/d/5/cd5b3e57dea18e4fad43bd1b16d5ff8ddf3e88be.png)  
How do I know the hw flow control (CTS, RTS) work normally?

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<div class="post-metadata">

**Author:** ![KevinFFF](https://sea2.discourse-cdn.com/nvidia/user_avatar/forums.developer.nvidia.com/kevinfff/32/15508_2.png) [@KevinFFF](https://forums.developer.nvidia.com/u/KevinFFF)\
**Post date:** [October 25, 2023, 7:31am UTC](https://forums.developer.nvidia.com/t/uart1-hw-flowcontrol-behavior-is-abnormal/270358/5 "2023-10-25T07:31:17Z")

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May I know what’s your use case with HW flow control?  
Do you connect any UART device or transfer large data?

You may use `stty` command to configure UART and use `cat` `echo` command to verify UART in loopback test.

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<div class="post-metadata">

**Author:** ![system](https://sea2.discourse-cdn.com/nvidia/user_avatar/forums.developer.nvidia.com/system/32/68080_2.png) [@system](https://forums.developer.nvidia.com/u/system)\
**Post date:** [November 20, 2023, 6:31am UTC](https://forums.developer.nvidia.com/t/uart1-hw-flowcontrol-behavior-is-abnormal/270358/7 "2023-11-20T06:31:23Z")

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