Uefi watchdog

Robotics & Edge Computing Jetson Systems Jetson AGX Orin
1

Hello,

I am currently working on enabling a watchdog in UEFI on the NVIDIA Jetson AGX Orin platform.

From my understanding, there is a default software watchdog enabled in UEFI with a timeout of 5 minutes configured by CONFIG_BOOT_WATCHDOG_TIMEOUT. I am attempting to replace this with the CCPLEX hardware watchdog by using the ARM watchdog UEFI driver, configured as follows:

CONFIG_ARM_WATCHDOG=y

CONFIG_ARM_WATCHDOG_CONTROL_BASE=0x02190000

CONFIG_ARM_WATCHDOG_REFRESH_BASE=0x02090000

CONFIG_ARM_WATCHDOG_INTERRUPT=7

These addresses were taken from the Jetson Orin SoC Technical Reference Manual, for the CCPLEX watchdog, the same used during kernel boot.

However, when applying this configuration, the boot process crashes. The logs indicate a data abort due to a translation fault when accessing the memory region at 0x02190000, suggesting that the region is not properly mapped or accessible in UEFI:

Data abort: Translation fault, second level
FAR 0x0000000002190000

Based on this behavior, I would like to clarify the following points:

  • Can you confirm that the default watchdog in UEFI is a software watchdog?
  • Is it possible to enable and use the CCPLEX hardware watchdog within UEFI on Jetson AGX Orin?
  • If so, what is the correct way to map and access the CCPLEX watchdog registers in the UEFI environment?

Any guidance or examples would be greatly appreciated.

Thank you in advance for your support.

4

Hi lroca,

Are you using the devkit or custom board for AGX Orin?
What’s the Jetpack version in use?

The stock Jetson AGX Orin UEFI does include a build-time boot watchdog with a default timeout of 5 minutes, but Jetson public UEFI configs do not enable CONFIG_ARM_WATCHDOG by default.
So replacing the default boot watchdog by only setting CONFIG_ARM_WATCHDOG_* to the CCPLEX TRM addresses is not sufficient on Jetson.
The translation fault at 0x02190000 strongly suggests the MMIO region is not mapped into UEFI and/or access is blocked by platform firewall/SCR configuration.
On Jetson, this typically requires a custom UEFI port: updating the UEFI platform DTB/overlay or platform resource description, and also checking MB1/MB2 BCT, SCR, and firewall settings for CCPLEX access.

5

Hi Kevin,

Thanks for the details. To answer your earlier questions: I’m using a custom carrier board for AGX Orin, and the JetPack version is L4T R36.4.3.

A few follow-ups on the uefi watchdog:

  1. When you refer to the build-time boot watchdog with the default 5-minute timeout, is that the same one configured via CONFIG_BOOT_WATCHDOG_TIMEOUT? From reading the code, this appears to be a software watchdog driven by UEFI events rather than a hardware watchdog. Can you confirm that understanding is correct?

  2. If it is indeed a software watchdog, is there a UEFI driver that drives an actual hardware watchdog on Orin?

Thanks again for your help.

6

Yes, CONFIG_BOOT_WATCHDOG_TIMEOUT is the timeout setting for the UEFI boot watchdog, which is implemented by BootWatchdog.c.
It is separate from the hardware-watchdog path enabled by CONFIG_ARM_WATCHDOG, whose UEFI driver is GenericWatchdogDxe (ARM SBSA watchdog).

7

Hi Kevin,

Thanks for the clarification. In that case, would the GenericWatchdogDXE (ARM SBSA watchdog) driver be compatible with the CCPLEX hardware watchdog?

8

Not necessarily. GenericWatchdogDxe is intended for an ARM SBSA-compliant watchdog, not for an arbitrary platform-specific watchdog block.